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MathWorks launches HDL Coder and HDL Verifier.

TELECOMWORLDWIRE-March 2, 2012-MathWorks launches HDL Coder and HDL Verifier(C)1994-2012 M2 COMMUNICATIONS

Mathematical computing software company MathWorks on Friday announced two new products that support HDL code generation and verification across MATLAB and Simulink.

HDL Coder automatically generates HDL code from MATLAB, which enables engineers to implement FPGA and ASIC designs from the widely used MATLAB language, while HDL Verifier includes FPGA hardware-in-the-loop capabilities for testing FPGA and ASIC designs.

MathWorks said HDL Coder generates portable, synthesizable VHDL and Verilog code from MATLAB functions and Simulink models that can be used for FPGA programming or ASIC prototyping and design, enabling users to immediately identify the best algorithm for hardware implementation. Traceability between Simulink models and generated HDL code also supports the development of high-integrity applications that adhere to DO-254 and other standards.

HDL Verifier now supports FPGA hardware-in-the-loop verification for Altera and Xilinx FPGA boards. It provides co-simulation interfaces that link MATLAB and Simulink with Cadence Incisive, Mentor Graphics ModelSim and Questa HDL simulators.

Both HDL Coder and HDL Verifier are available, with US list prices for HDL Coder starting at USD10,000, while HDL Verifier is priced from USD3,250.

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Date:Mar 2, 2012
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