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Massana's New FILU Development System Speeds Prototyping, Time-to-Market; Supports General-Purpose, Industry-Standard RISC Processors.

ORLANDO, Fla.--(BUSINESS WIRE)--Nov. 1, 1999--

Massana Inc., an emerging semiconductor IP (SIP) company, has unveiled a FILU Development System that enables System-on-Chip (SoC) designers to easily evaluate any member of its FILU family of DSP coprocessor cores, thereby rapidly accelerating prototypes of their IC designs and speeding time-to-market of their proprietary products.

Massana's FILU Development System, to be demonstrated at DSP World this week in Massana's Booth No. 411/412, allows combining these Massana DSP cores with industry-standard RISC processors. The FILU devices (the FILU-200, FILU-50, and FILU-50HC11) are implemented in an FPGA and are clocked at 20MHz. All members of the FILU family of DSP coprocessor cores are available for licensing worldwide.

The FILU Development System is designed in modular form to interface with several popular RISCs. The Development System enables designers' to verify their hardware, software, and algorithms. Also, the algorithms can be developed using the Instruction Set Simulator provided and later executed in the target system in real time.

First application of the FILU Development System is for a G.Lite reference design for Massana's recently unveiled FILU-DMT, a low-cost G.Lite DSP coprocessor core. This reference design consists of the FILU-DMT DSP coprocessor core on a PC PCI card with a G.Lite AFE and DAA.

Other noteworthy FILU Development System features include a 16-bit stereo audio codec, prototyping area, LCD display, and RS232 interface. The stereo audio codec is provided for real-time application evaluation. The FILU interfaces with the codec using a synchronous serial interface (SSI). In addition, a prototyping area is provided for user-defined signal conditioning.

"Time-to-market windows are rapidly shrinking," noted Brian Murray, Massana's Vice President of Engineering, and a company co-founder. "With that in mind, we've provided the FILU Development System. It's all about speed: rapid development, rapid prototyping, and rapid market delivery. The availability of this system allows OEMs and chipmakers alike to proceed swiftly with some of their most advanced IC designs."

A three-year-old company, Massana has successfully transformed itself from a provider of VLSI design services into a SIP company. As part of this new strategic direction, the company has relocated its corporate headquarters to Silicon Valley.

Following its initial FILU series of low-cost DSP compute engines, Massana plans to release a Fast Ethernet PHY core, and is also developing a Gigabit Ethernet PHY core.

Massana's mission is to provide lightning-fast bandwidth via its proprietary silicon solutions for standards-based communications and networking systems. These solutions are delivered through patented DSP module compiler technology coupled with proprietary DSP algorithms. Among the company's clients/partners are Alcatel, Analog Devices, Motorola, Nortel, and Toshiba.

For more information, contact Irving Gold at Massana Inc., 51 E. Campbell Avenue, Campbell, CA 95008; Phone: 408/871-1415; Fax: 408/871-2414; Or Ben O'Sullivan (Europe), +353 1 604 0158; Fax: +353 1 602 3977; Or visit the company on the Internet at
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Publication:Business Wire
Date:Nov 1, 1999
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