Printer Friendly

Marvell Semiconductor 88C3000 And 88C3100 Fact Sheet.

SAN JOSE, Calif.--(BUSINESS WIRE)--Aug. 25, 1998--Competitive highlights for Marvell's 88C3000 and 88C3100 PRML read channels include the smallest chip size on the market (12 mm2), highest data rate with lowest power dissipation, migratable architecture and nearly 100 percent test coverage.
88C3000 and 88C3100

-- Support data rates from 70 Mb/s up to 350Mb/s with a clear path
 for HDD integration and data rates beyond 700Mb/s.

-- Provide increased performance at process technology milestones
 without compromising time-to-market.

-- Maintain constant architecture of proven designs with minimal pin
 and register changes to significantly reduce drive development
 time as process technology migrates.

-- Ensure excellent signal-to-noise (SNR) performance with over 2dB
 gain for EPR4 and 4dB for Noise Predictive Viterbi (NPV) compared
 to PR4, and support user bit densities (UBD) in a range from 1.8
 to 3.0.

-- Offer automated channel optimization tools for ease-of-use and
 hands-on technical support throughout disk drive development.

-- Provide robust signal conditioning capabilities with a 7-pole
 anti-aliasing low pass filter, 6-bit flash A/D converter, 5-tap
 programmable digital FIR followed by a 3-tap
 adaptive/programmable FIR.

-- Include a precision charge pump and loop filter for timing
 recovery with no external components required.

-- Offer synchronous and asynchronous servo modes and up to 6-burst
 servo demodulation accessible as either analog signals or 10-bit
 digital values.

-- Operate both in 3.3V and 5V environments.


The 88C3000 family in 0.35 microns CMOS is designed with highest data rates in mind. It comprises the 88C3000 100-pin TQFP package with data rate at 350 Mb/s and the lower cost version 88C3020 64-pin TQFP running at 300 Mb/s. Power dissipation for the 88C3000 scales linearly with data rate and typically consumes 1.0W at 350 Mb/s. The 88C3000 has a selectable PR4 and EPR4 Viterbi with 8/9 or 16/17 ENDEC and is designed for user bit densities (UBD) of 1.8 to 2.5.


The 88C3100 is the sister product of the 88C3000 that implements 85% of 88C3000 circuitry plus significant enhancements such as a full 16-state NPV with trellis code slated for UBD of 2.5 and higher. The 88C3100 family comprises the 88C3100 100-pin TQFP package with a data rate at 300 Mb/s and the lower cost version 88C3120 64-pin TQFP running at 250 Mb/s. The 88C3100's 2dB gain in SNR means increased linear density (bits per inch) which automatically translates to higher capacity per drive.
 Competitive Analysis of Current High Performance PRML Channels

 Product Analog CMOS BiCMOS Marvell's 88C3000 Marvell's 88C3100
 Family Family
 Process 0.35 0.35 0.35 0.35
 microns microns microns microns
 1P/2M 1P/2M
 Digital CMOS Digital CMOS
 Data 240 200-320 350 300
 Power greater than greater than
@Data rate 0.6W @ 0.6W @
 200 Mbits/s 200 Mbits/s

 greater than greater than 1.0W 1.1W
 1.7W 1.7W 350 Mbits/s 300 Mbits/s
 240 Mbits/s 300 Mbits/s
 Chip Area 14-20 mm2 14-24 mm2 less than 12 mm2 less than 14 mm2

 (Sources: Marvell, IEEE & Data Storage)

Note to Editors: A chart showing total power dissipation measurements is available upon request.

CONTACT: Pacifico, Inc.

Patricia Colby, 408/293-8600


Marvell Semiconductor, Inc.

Matt Ahangi, 408/222-2542
COPYRIGHT 1998 Business Wire
No portion of this article can be reproduced without the express written permission from the copyright holder.
Copyright 1998, Gale Group. All rights reserved. Gale Group is a Thomson Corporation Company.

Article Details
Printer friendly Cite/link Email Feedback
Publication:Business Wire
Date:Aug 25, 1998
Previous Article:NetVital Launches ReplicateNow! Universal Data Replication Software.
Next Article:Interlink Electronics Signs Licensing Agreement With Sanyo Electric, Seiko Epson and Matsushita.

Related Articles
Marvell Semiconductor Inc. signs distribution agreement with Yamaha Corp.; teaming with Yamaha offers Marvell access to Japanese market, synergistic...
Marvell Semiconductor Adds 240 Mb/s User-Switchable EPR-4/PR4 PRML Read-Channel Devices, Improves Density; Marvell's Digital CMOS Designs Continue to...
Marvell Announces High Performance Mixed-Signal Integrated Circuits for the Mass Storage Market.
Marvell Semiconductor Names Gordon Steel as Vice President Finance and Chief Financial Officer; Mixed-signal IC Company Welcomes Industry Veteran.
Marvell Semiconductor Appoints Dr. LeeChung Yiu as Vice President of Engineering.
Marvell Enters Broadband Data Communications Market With Leading-Edge Mixed-Signal IC Solutions for High-Speed Ethernet.
Marvell Announces the World's First and Most Advanced 8-Port DSP Fast Ethernet PHY Transceiver.
Marvell Appoints New Chief Financial Officer.
Marvell Technology Group Ltd. Opens Regional Headquarters and Advanced Technology Design Center in Singapore to Support Expanding International...
Marvell Technology Group Ltd. and Galileo Technology Ltd. Announce Shareholder Approval of Pending Merger.

Terms of use | Copyright © 2017 Farlex, Inc. | Feedback | For webmasters