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MIPS Technologies, Inc. Enhances Architecture to Support Growing Need for IP Re-Use and Integration.

MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--May 3, 1999--

New MIPS32 and MIPS64 Architectures Combine Best of

Existing 32- and 64-bit ISAs to Create a Stronger

Foundation for Embedded Developers

MIPS Technologies, Inc. (Nasdaq:MIPS) today announced an evolution of its architectural framework for MIPS(R) processors.

The new MIPS32(TM) and MIPS64(TM) architectures incorporates previous MIPS(R) instruction set architectures, or ISAs, add new more powerful instructions, and expand the MIPS(R) standard to include privileged mode and kernel operations used in operating system software.

These two new standards represent the foundation for all future MIPS(R) processor related development while supporting all legacy IP (intellectual property). They have been defined as part of the company's strategy to address two key issues facing embedded developers: IP re-use and system-on-chip integration.

"These new architecture definitions should strengthen MIPS Technologies' position in the high performance embedded market," said Tom R. Halfhill, a senior analyst at MicroDesign Resources, which publishes the Microprocessor Report.

"By combining the best parts of the existing MIPS(R) instruction sets with some very useful extensions, the MIPS32(TM) and MIPS64(TM) architectures provide new options to embedded-system designers who need high performance in a customizable processor.

"Both architectures should be well suited for system-on-a-chip solutions. MIPS Technologies is obviously positioning itself to take advantage of the emerging markets for new kinds of low cost information appliances and personal computing devices."

Developer tool vendors will clearly benefit from the new standards. The new architectures simplify and standardize the underlying mechanisms used in supporting real-time software, and it enables vendors to efficiently craft a single set of development tools that support MIPS-based(TM) processors. This will lower the cost and speed the development of new tools for the MIPS(R) processor market.

"As the leader of the MIPS(R) architecture alliance, we must ensure that the market has the standards it needs to support growth," said Lavi Lev, senior vice president of engineering for MIPS Technologies, Inc.

"These new architectures provide a powerful and stable platform to supports high performance 32-bit embedded applications and provide a seamless upgrade to the 64-bit level. They lower the cost of developing MIPS-based(TM) systems and enable the reuse of hard-earned development expertise across multiple designs."

The new MIPS32(TM) and MIPS64(TM) architecture standards build on 15 years of MIPS(R) processor experience. During this time, the MIPS(R) architecture has become the leading embedded 32-bit and 64-bit RISC architecture because of its robust instruction set, extensible architecture, its scalability from 32-bits to 64-bits and the widespread support from numerous licensees of MIPS Technologies.

The original MIPS I(TM) ISA has evolved into the MIPS II(TM), MIPS III(TM), MIPS IV(TM) and MIPS V(TM) ISA levels. MIPS Technologies, Inc. has taken advantage of the experience from the past 15 years and developed the new MIPS32(TM) and MIPS64(TM) architectures.

The MIPS32(TM) architecture incorporates all of the 32-bit MIPS I(TM) and MIPS II(TM) ISAs with the addition of features from popular 64-bit R4000(R) and R5000(R) processor families. These include conditional moves, prefetch instructions, privileged instructions and other enhancements.

In addition, DSP enhancements such as multiply (MUL) and multiply and add (MADD) instructions have been standardized and added to the new architectures. While these instructions have been available as licensee-specific extensions in the past, this is the first time that they have been available as a standard part of the MIPS(R) architecture.

The MIPS64(TM) architecture incorporates the latest MIPS V(TM) 64-bit ISA with the addition of the standardized MADD and MUL instructions. MIPS64(TM) provides full support of 64-bit floating point co-processors and support for flexible instruction and data caches.

It is a superset of the MIPS III(TM), MIPS IV(TM), and MIPS V(TM) ISAs. In addition, it adds a MIPS32(TM) mode so that all MIPS32(TM) code will run on a MIPS64(TM) architecture platform. This ensures upgrades from 32-bit to 64-bit processors are fast and seamless.

This simplifies the task of upgrading systems from 32-bit to 64-bit operation, enables reuse of intellectual property and ensures interoperability for the future. The MIPS64(TM) architecture is well-suited for applications that need to process large databases and streaming data types such as audio and video.

Both architectures include a consistent privileged mode and cache access control mechanisms. One of the advantages of the MIPS(R) architecture is flexible cache configurations that let developers choose the most appropriate cache implementation based on system performance requirements, power constraints and component costs.

These new cache control instructions make cache implementations consistent and easier to manage, and development of real-time operating system software is simpler. Development tool vendors can now develop one set of kernel software for use across many platforms. This reduces the development time and cost of supporting multiple MIPS(R) processor implementations.

The first implementations of the new architecture are the MIPS32(TM) 4Kc(TM) (code named Jade) core licensed by Texas Instruments (see press release dated 2/16/99), and IDT's RC32364(TM). Later this year, the MIPS64(TM) 20K(TM) family (code named Ruby) will be available.

About MIPS Technologies, Inc.

MIPS Technologies, Inc. licenses its intellectual property to semiconductor manufacturing companies, ASIC developers, and system OEMs. MIPS Technologies, Inc. and its licensees offer a wide range of robust, scalable processors in standard, custom, semi-custom and application-specific products.

Developers can choose from a broad menu of price/performance options that include execution units, clock speeds, instruction widths (16-, 32- or 64-bit), cache sizes, memory bandwidths, memory protection schemes, system interfaces, and on-chip system logic.

Licensees currently include: ALCHEMY (Cadence); Broadcom Corp.; CommQuest (IBM); Integrated Device Technology, Inc. (IDT); LSI Logic Corp.; Macronix; NEC Corp.; NKK Corp.; Philips Semiconductors; Quantum Effect Design, Inc. (QED); Sony Corp.; Synova; Texas Instruments Inc.; and Toshiba Corp.

Numerous companies utilize MIPS intellectual property. MIPS Technologies, Inc. is based in Mountain View, and can be reached at 650/567-5000 or

Note to Editors: MIPS is a registered trademark of MIPS Technologies, Inc. MIPS-based, MIPS32, MIPS64, 4K, 4Kc, 4Kp are trademarks of MIPS Technologies, Inc. All other trademarks are the property of their respective companies. is a trademark and the R3000 and R4000 are registered trademarks of MIPS Technologies, Inc. All other trademarks are the property of their respective companies. All press materials are available on the World Wide Web via:


Semico Research Corp.

"MIPS Technologies, Inc. once again anticipates the needs of the embedded market," said Tony Massimini, chief of technology at Semico Research. "The MIPS(R) RISC processor family has been widely recognized as the most easily scalable architecture and now they have made that process even easier with these new standards.

"The system developer benefits the most by being able to reuse their development IP on one project to many others. They can invest in an entry-level 32-bit system and integrate that investment into later, higher performance 64-bit systems. This can be a decided advantage in an emerging market where product features tend to expand rapidly and market pressures demand quick introduction of next generation systems."


"We support this effort by MIPS Technologies, Inc. to standardize the next generation MIPS(R) RISC architecture," said Nick Kucharewski, vice president of IDT's microprocessor division.

"Everyone gains by expanding the architecture standards to include popular features, such as multiply and multiply-add, which were previously only implemented in specific processors such as IDT's RC4640(TM). In addition, we are already supporting the MIPS32(TM) architecture with our RC32364(TM) device, now shipping in production, and expect to support the MIPS64(TM) in the future."


"There is no doubt that these new standards will help position the MIPS RISC industry as the leading processor choice in high performance embedded systems," said Andy Keane, vice president of marketing at Quantum Effect Design, Inc. "We applaud MIPS Technologies, Inc. for taking the lead in defining these new architectures."

Integrated Systems, Inc.

"Embedded system software depends upon the underlying control mechanisms to keep kernel software safe from inadvertent writes," points out David Stepner, vice president of product development of Integrated Systems, Inc.

"With these new privileged mode standards, we can now develop a standard MIPS(R) RISC processor kernel and apply it across all of the 32-bit and 64-bit MIPS-basedTM processors. This is an advantage for us and our customers."


"MIPS-based(TM) processors have always been the choice for high performance embedded 64-bit applications," notes Don Langley, vice president, semiconductor segment sales, Cygnus Solutions. "Now the development work done on 32-bit platforms can be easily ported for use on 64-bit processors. This will widen our market and make our GNUPro(R) tools and eCos operating system easier to maintain."

Wind River Systems, Inc.

"MIPS Technologies, Inc. is to be commended for acting in a pro-active manner in developing these new standards," says David Sheaffer, director of hardware platforms, Wind River Systems. "The existing ISAs provided a viable bridge from 32-bits to 64-bits, but these new architectures help everyone by standardizing the best features for both in-system performance and support tools.

"They have taken the experience gained by the MIPS(R) RISC industry and incorporated it into a new standardized framework for the benefit of both tool developers and users. The result will be improved MIPS support from Wind River and its many partners, which will benefit the MIPS community at large."
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Publication:Business Wire
Geographic Code:1USA
Date:May 3, 1999
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