MAGMA BLAST FUSION DELIVERS TWO FULL-CHIP DESIGNS FOR FUJITSU NETWORK COMMUNICATIONS.
"We believe that by working with Texas Instruments and Magma, we saved at least two months of critical development time in the completion of the physical design of these chips," said Tom Brown, senior director of ASIC Design at Fujitsu Network Communications. "Magma's Blast Fusion technology has demonstrated its ability to complete challenging designs. These chips are operational and demonstrate first-pass success in our systems today."
"We recently completed full deployment of Blast Fusion to our worldwide design centers," said Francis Larochelle, CAD Development manager, for the ASIC division at TI. "Cycle time and predictability of timing closure are extremely important for our focused ASIC business. By completing these chips and meeting the expected performance goals, we have validated Blast Fusion's ability to deliver predictable timing closure on large complex, high-performance, full-chip designs. We are seeing that Blast Fusion is capable of handling our most complex top-level designs and currently have several chips being done with Blast Fusion today."
An early Magma adopter, TI has been instrumental in shaping enhancements to the Blast Fusion system. With Blast Fusion, TI has achieved significantly improved runtimes over traditional physical design tools for logic optimization, placement and routing. Through Magma's Early Silicon Performance (ESP) capability, Blast Fusion also provided TI with accurate timing information much earlier in the design flow. This enabled TI to quickly determine the timing feasibility of their customer's designs prior to beginning layout. Certain that Fujitsu's designs would now meet the required timing specifications, the TI-Magma design team was able to quickly take the complex designs from netlist to clean GDSII without struggling through numerous synthesis-to-layout iterations.
"By working with leading ASIC vendors such as Texas Instruments, we continue to improve our system to meet the demands of today's ASIC design flow," said Bob Smith, vice president of product marketing for Magma. "By giving the ASIC designer early visibility into the expected timing performance of their design, our products reduce `false starts' on physical design that often lead to lengthy iteration cycles. The ASIC vendor benefits by getting more fully qualified designs at the outset and having a robust system for full-chip design and assembly that delivers the desired circuit timing."
Conventional place and route flows can't take timing constraints into consideration until late in the flow, so designers often do not complete them prior to beginning physical design. This often results in additional iterative cycles. Blast Fusion utilizes Magma's patent-pending FixedTiming methodology and single, unified data model architecture, which allow it to perform logic optimization and physical design while taking timing constraints into account. This unique approach enables Blast Fusion to provide designers with accurate timing information prior to detailed layout and to significantly reduce iterations between synthesis and place & route. Additional timesavings can be accomplished by using Blast Logic, Magma's timing constraint sign-off tool, prior to starting physical design.
The completion of the Fujitsu ASIC designs is a significant milestone in TI's deployment of Blast Fusion to its worldwide design centers. They are representative of more than 40 designs that have now been completed in TI ASIC CDCs worldwide using Blast Fusion. TI has repeatedly demonstrated that given a final netlist and complete timing constraints, Blast Fusion can significantly reduce the logic optimization and physical design process.
Magma software products enable chip designers to reduce the time required to design and produce complex integrated circuits in the communications, computing, consumer electronics, networking and semiconductor industries. Magma provides a single executable for RTL-to-GDSII chip design. The company's products, Blast Fusion, Blast Chip, Blast Plan, Blast Noise and Blast Prototype utilize Magma's proprietary FixedTiming methodology and single data model architecture to reduce the timing-closure iterations often required between the logic and physical processes in conventional IC design flows. Magma's Diamond SI also leverages the single data model architecture to provide an integrated, standalone platform for post-layout, sign-off-quality signal integrity verification.
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|Comment:||MAGMA BLAST FUSION DELIVERS TWO FULL-CHIP DESIGNS FOR FUJITSU NETWORK COMMUNICATIONS.|
|Publication:||EDP Weekly's IT Monitor|
|Date:||Jul 15, 2002|
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