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Lucent Technologies Offers New ATM and PCI Software Cores for Field-Programmable Gate Array -FPGA- Chips.

ALLENTOWN, Pa.--(BUSINESS WIRE)--Aug. 18, 1998--Lucent Technologies' Microelectronics Group today announced availability of two new ATM software cores for its ORCA(r) field-programmable gate arrays (FPGAs) and updates to three other ATM and PCI cores that the company introduced last year.

Called Customer Solution Cores (CSCs), these pre-coded, pre-tested, and pre-verified building blocks let manufacturers of data communications and telecommunications network equipment incorporate ATM and PCI functions into their specific designs. The cores provide a wider choice of features, such as different interfaces and control logic, than are available in standard, off-the-shelf chips. They also offer faster FPGA design cycles for improved time to market, design flexibility using built-in interface and function options, and source code for easy design integration and modification.

Newly offered are two ATM available bit rate (ABR) CSCs from Modelware: the ABR resource management (RM) cell processor, and the ABR RM cell manager. These cores work in conjunction with Lucent's ATLANTA(tm) ATM-switch chip set to provide resource management cell relative rate and explicit rate marking according to the Bell Laboratories Dynamic Maximum Rate Control Algorithm (DMRCA) or a user-provided proprietary algorithm.

Updates to Modelware's ATM UTOPIA I/II Slave and ATM UTOPIA I/II Master CSCs for ORCA FPGAs increase operating speed from 33 megahertz (MHz) to 50 MHz. Updates to Lucent's PCI Master CSC demonstrate 50 MHz performance, add new pinouts for compatibility with Lucent's new OR3TP12 66 MHz embedded-core PCI field-programmable system chip (FPSC), and upgrade the CSC for use with the most recent releases of synthesis and ORCA Foundry software. In addition, Modelware continues to offer its ATM physical layer CSC for ORCA FPGAs and Lucent continues to offer its PCI Target CSC for ORCA FPGAs.

"With these additions and updates to our CSC product line, we make it easier for communications systems designers to put the latest capabilities into their products in a timely manner," said Barry Britton, Lucent's strategic marketing and product planning director for FPGAs. "We also offer equipment manufacturers the best value by including a complete design solution with source code packaged at a price that's lower than what many vendors charge for their fixed macros without source code."

The new Customer Solution Cores and updates are the latest in Lucent's versatile line of field-programmable IC offerings. In May, Lucent announced its field-programmable system chip, a device that combines mask-programmed standard-cell logic and field-programmable gate array logic on a single slice of silicon. Lucent's FPSCs, which begin shipping next month, offer the component density, high performance and increased functionality of standard-cell logic with the advantages of programmability for faster development and timely delivery of new system features.

All CSCs support 2C/TxxA ORCA devices and third-party simulation and synthesis tools. The CSCs come with a complete design solution package that includes VHDL source code and test bench (Verilog for PCI Master CSC); scripts and data files for simulation, synthesis and FPGA layout; and detailed documentation.

The new and updated Customer Solution Cores are available now. The ATM Customer Solution Cores are available directly from Modelware. PCI CSCs are available from Lucent Technologies. Pricing for U.S. customers is as follows:

ATM UTOPIA I/II slave - $8,000 ATM UTOPIA I/II master - $11,000 ATM ABR RM cell manager - $30,000 ATM ABR RM cell processor - $50,000 ATM physical layer - $30,000 PCI master - $7,995 PCI target - $4,495

For product literature, customers may call the Lucent Technologies Customer Response Center Microelectronics, at 1-800- 372-2447, Dept. R41 (in Canada, 1-800-553-2448, Dept. R41); fax number 1-610-712-4106 (especially for callers outside of North America); or write to Lucent Technologies, Room 30L-15P, 555 Union Blvd., Allentown, Pa. 18103. Product literature is also available on the web at

For further information about the ATM CSCs, customers may also contact Modelware directly at 1-732-389-1922; fax number 1- 732-389-2735; or write to Modelware, 18 Polo Club Drive, Suite 24, Tinton Falls, N.J. 07724. Modelware provides advanced synthesizable cores and design services to the telecom industry. Product literature and other information on the company is available on the web at

Lucent Technologies designs, builds and delivers a wide range of public and private networks, communications systems and software, data networking systems, business telephone systems and microelectronics components. Bell Laboratories is the research and development arm for the company. For more information on Lucent Technologies, headquartered in Murray Hill, N.J., USA, visit its web site at

Lucent's Microelectronics Group designs and manufactures integrated circuits and optoelectronic components for the computer and communications industries. More information about the Microelectronics Group is available from its web site at

Additional Technical Information

The ATM UTOPIA Master CSC implements the ATM Forum's UTOPIA Level 1 and Level 2 specifications. The CSC interfaces to the application (e.g. ATM physical or adaptation layer via a generic FIFO-like access interface, and to multiple physical layer ports via a UTOPIA Level 1 or Level 2 interface. The CSC monitors, in a round-robin fashion, a programmable range of PHY ports and reports their cell-available status to the ATM layer. The ATM layer issues a command to the UTOPIA Master CSC to select a PHY port and initiate cell transfer to that port.

The ATM UTOPIA Slave CSC features Level 1 and Level 2 parity generation and checking, multi-PHY mode support, and 25-MHz, 33- MHz or 50-MHz operation. Both cores feature FIFO control and monitoring, and can use either 128 x 9 internal ORCA FIFOs or external 9-bit IDT722x1-type FIFOs. The standalone UTOPIA core can also operate with 16-bit datapaths and thus can use 64 x 17 internal ORCA FIFOs or 18-bit IDT7221x1-type FIFOs. The ATM physical layer core can be implemented in an OR2C/2T15A with external FIFOs or an OR2C/2T26A with internal FIFOs, and the standalone UTOPIA core can be implemented in an ORC2C/2T08A with external or internal FIFOs.

The ABR Resource Management (RM) Cell Processor (RMCP) operates in conjunction with the Lucent Technologies ATM layer Manager (ALM) and ATM Buffer Manager (ABM) to provide a complete solution for ABR switch processing in compliance with the ATM Forum's Traffic Management 4.0 specification. The RMCP implements Bell Labs' Dynamic Maximum Rate Control Algorithm (DMRCA) for ABR. The ABR Resource Management (RM) Cell Manager (RMCM) CSC provides a framework for a user-provided RM cell-marking algorithm instead of the DMRCA algorithm to perform the ABR function.

The ORCA PCI Master/Target CSC provides a complete implementation of a 33 MHz, 32-bit Master/Target interface, compliant to the PCI V2.1 Local Bus Specification. The package includes bidirectional buffering on the master bus, and both the master and target interfaces support full-burst, no-wait-state performance when both sourcing and receiving data. Many other features are supported, such as dual-address, 3.3V and 5V signaling and several optional configuration registers. Complete Verilog source code is supplied, as are test benches and scripts to automate the design process through Synopsys and Exemplar design flows. Also included is a sample design demonstrating ORCA's ability to implement a 50 MHz PCI full-featured solution. Documentation included makes it easy to merge the unit into the final system on an FPGA.

CONTACT: Carl Blesch

908-508-8412 (office)

908-306-0784 (home)


Tom Topalian

908-508-8673 (office)

908-904-4318 (home)
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Date:Aug 18, 1998
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