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Long channel carbon nanotube as an alternative to nanoscale silicon channels in scaled MOSFETs.

1. Introduction

Carbon nanotubes (CNTs) are gaining momentum in the current silicon technology as a complementary nanostructure that could reform the device architecture. CNT modeling has been rigorously studied and examined [1-5] to assess the performance of the device at the circuit level. Advancement of the nanotechnology devices modeling is vital for the foreseeable future of carbon nanotube as switching device, interconnect and memory in integrated circuits (ICs). An in situ growth single-walled carbon nanotube (SWCNT), which integrates long channel 600 nm CNT channel, thin [Al.sup.2][O.sup.3] top gate contact, and Palladium (Pd) metal source/drain contacts, has been demonstrated [6].

In addition, we report the potential of long channel 65 nm CNT as substitute to 45 nm silicon metal-oxide semiconductor field-effect transistor (Si MOSFET) from the perspective of modeling for future CNT-logic applications. We observe good agreement between CNTFET and Si MOSFET respectively, when simulating two-terminal drain current-voltage ([I.sub.d] - [V.sub.d]) characteristic. The projection has shed light on the reduction of DIBL and high field effects [7] as well as reduction in long channel CNT which is a widespread phenomenon in nanoscale Si MOSFET [8, 9]. We also demonstrate the effects of the channel area restructuring on the maximum electric field as well as density of states (DOS) in the conductance of CNT. Unlike MoSfET, it is revealed that the performance of CNT is enhanced when the source and drain width is minimized rather than the length, primarily due to the gate-to-source-drain parasitic fringe capacitances [10]. MOSFET scaling in accordance with Moore's Law will reach its fundamental limitation as a result of process controllability in the next 10 years. Consequently, it is necessary to ensure that novel material is studied to provide alternatives to the current technologies and challenges in the new era of nanotechnology.

2. Carbon Nanotube and MOSFET Modeling

The layout of a CNTFET device is depicted in Figure 1. The area of the channel is given by the multiplication of the width, W, of the source and drain contact and the length, L, of the nanotube [6]. Details of the quasiballistic MOSFET device modeling can be found in previous work in [11,12]. The carbon nanotube model [13] is a unified nanostructure model based on quantum transport theory established by Datta [14]. This work extended the universal DOS spectral function [15] into the numerical calculation for CNT conduction subbands. We have included multiband density of states to account for multimode transport [16]. For an accurate simulation, the input parameters shown in Table 1 for MOSFET and CNTFET are extracted from TSMC [17] and Javey et al. [18], respectively. The 60 nm nanotube device model incorporate quasiballistic transport scattering as confirmed by [18]. At 60 nm length, the carriers travelling on the CNT surface have smaller mean free path than acoustic phonon which occurred at 300 nm.

The typical width of a high-tech CNTFET device is reported [10] to be 1 [micro]m. The width of the CNT is calculated to be [W.sub.CNT] = [A.sub.MOS]/[L.sub.C], when both CNT and MOSFET devices are having identical channel area ([A.sub.MOS] = [A.sub.CNT]). In a case when both devices can provide same level of current, channel area becomes A = [(kL).sup.2] when given the scaling factor; k and both parameter W = L. CNT channel with length, 2 k[L.sub.CNT], can provide the same current with [W.sub.CNT] = 0.5 L CNT. Even when the physical widths of the CNT channel, W [less than or equal to] 0.5 k[L.sub.CNT], there is no area drawback provided L [greater than or equal to] 2 k[L.sub.CNT]. As nanotube channel length increases, maximum electric field in CNT, [E.sub.mCNT] reduces tremendously [19, 20]. As for CNT with L = 60 nm, the maximum electric field is found to be [E.sub.m] = (3/4)[E.sub.mSi].

In the [I.sub.d] - [V.sub.d] simulation of CNTFET, Landauer-Buttiker formalism is utilized [21]. The drain current, [I.sub.d] is given as


where [G.sub.ON] is the ON-conductance, [] is the channel potential, [E.sub.f] is the Fermi energy, [k.sub.B] is the Boltzmann Constant, T is the temperature, q is the charge of an electron, VG is the gate voltage, [V.sub.d] is the drain voltage, and [V.sub.s] is the source voltage.

The quantum conductance limit of a ballistic SWCNT is [G.sub.ON] = 4[q.sup.2]/h. The theoretical framework of (1) derivation can be found in [19, 20]. The quasi-one-dimensional (Q1D) density of state function of CNT [22] is given by

D (E) = 2[g.sub.v][g.sub.s]/3[pi][]t[summation over (i)]E/[square root of ([E.sup.2] - [([E.sub.G]/2).sup.2])], (2)

where [] = 1.42[angstrom] and t = 3 eV is the carbon-to-carbon (C-C) bonding energy, EG is the bandgap energy, [g.sub.s] is the spin degeneracy, and [g.sub.v] is the valley degeneracy. On the other hand, the [I.sub.d] - [V.sub.d] characteristics for a short channel MOSFET can be expressed as

[I.sub.d] = [C.sub.G][[mu].sub.ef][W.sub.MOS]/2(([V.sub.G] - [V.sub.T]) - (1/2)[V.sub.d])[V.sub.d]/1 + [V.sub.d]/[V.sub.c], 0 [less than or equal to] [V.sub.d]/[V.sub.dsat], (3)

where [C.sub.G] is the gate capacitance, [[mu].sub.ef] is the gate-field dependent mobility, [V.sub.d sat] is the saturation voltage at the point of current saturation, [V.sub.c] is the critical voltage, and [V.sub.T] is the threshold voltage. At current saturation, (3) becomes

[I.sub.d sat] = [alpha][C.sub.G] ([V.sub.g] - [V.sub.T] - [V.sub.d sat]) W[v.sub.sat], [V.sub.d] [greater than or equal to] [V.sub.d sat], (4)

where [alpha] = [v.sub.D]/[v.sub.sat] is ratio of drift velocity, [v.sub.D] with saturation velocity and [v.sub.sat] at the drain [11, 23].

3. Results and Discussion

Figure 2 shows the density of states for Q1D of [20,0] zigzag CNT with three van Hove singularities. As the energy span widens, more electrons are capable of occupying the singularities pinned between source and drain Fermi levels.

In the [I.sub.d] - [V.sub.d] simulation, the source Fermi energy is set to be at 0.22 eV below the conduction band. Our simulation results in Figure 3 which comes from (1) indicate that the CNT is able to offer drain current performance comparable to a 45 nm Si MOSFET. Remarkably, the effective current per unit dimension yielded 53.5 times more of Si channel because of the small diameter tube.

The DIBL effects is suppressed fairly well for both devices with a slight advantage to CNT. Silicon demonstrated a superior subthreshold swing at 32.37 mV/dec, a value half of CNT. Although CNT has a lower on current, it sustains a high on-off ratio in 4 orders of magnitude. In addition to the device simulation, a SWCNT with a channel length of 600 nm is fabricated and shown in Figure 4. The Paladium contacts are made by electron beam lithography on SWCNT grown by thermal CVD from catalyst islands.

The Id-VG measurement was carried out on a back gate geometry [approximately equal to] 200 nm Si[O.sub.2] depicted in Figure 5. From Figure 3, the gate characteristic, [I.sub.d] - [V.sub.G], can be generated for the 60 nm CNT model and it is illustrated in Figure 6. The DIBL for the experimental data is at 1453 mV/V, while SS is estimated to be 664 mV/dec. Nevertheless, the 600 nm fabricated CNT is compensated by a high off-on ratio at 3.2 x [10.sup.4]. It is found that DIBL can be lowered by at least one order of magnitude by doping the source end region of the channel [24] or the whole CNT [25, 26].

4. Conclusion

It is revealed that long channel CNT can deliver drain current comparable to a MOSFET. The carrier density along the CNTFET is at least 50 times that of the Si MoSfET. In the same channel area, CNT has better control of short channel effect (SCE) than Si as it has lower [E.sub.m]. This brings an enormous advantage since lower [E.sub.m] has a smaller DIBL. A double gate or a cylindrical gate structure has the best control to suppress DIBL [27].Based on this, we could have lower offcurrent in the transistor. As a result, a CNT uses less power consumption as a switching device when operating at the same frequency as a MOSFET


MLPT thanks the Ministry of Higher Education Malaysia and the Universiti Teknologi Malaysia (UTM) for the award of advanced study fellowship leading to a Ph.D. degree at the University of Cambridge. This work is partially supported by UTM Research University Grant vot no. Q.J130000.2623.09J21 and Fundamental Research Grant Scheme (FRGS/2/2013/SG02/UTM/02/2). MLPT is also immensely grateful to Aun Shih Teh for providing the experimental data of SWCNT. The author also thanks the Research Management Centre (RMC) of UTM and Centre for Advanced Photonics and Electronics (CAPE), Cambridge, UK, for providing an excellent research environment to complete this work.


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Michael Loong Peng Tan

Faculty of Electrical Engineering, Universiti Teknologi Malaysia (UTM), 81310 Skudai, Johor, Malaysia

Correspondence should be addressed to Michael Loong Peng Tan;

Received 11 July 2013; Accepted 26 November 2013

Academic Editor: Chunyi Zhi

TABLE 1: Device model input and output parameter at
[V.sub.G] = 1V.

Parameter                                           CNT

Type                                              Zigzag
Structure                                           Q1D
Gate insulator thickness, [t.sub.ox]              1.1 nm
Channel length, L                                  60 nm
Channel width, W                                  675 nm
Channel area, A                        4.05 x [10.sup.-15] [m.sup.2]
Tube diameter, d                                 1.5437 nm
Chiral vector (n, m)                              (20, 0)
Maximum electric field, [E.sub.m]             075 [E.sup.mSi]
Maximum current, [I.sub.d max]                59.43 [micro]A
Carrier density, [I.sub.d max]/              42.8 [micro]A/nm
  (d or W)
DIBL                                            39.41 mV/V
Subthreshold swing, SS                         74.44 mV/dec
On-off ratio                                 9.2 x [10.sup.3]

Parameter                                         mosfet

Type                                               nmos
Structure                                           Q2D
Gate insulator thickness, [t.sub.ox]              1.1 nm
Channel length, L                                  45 nm
Channel width, W                                   90 nm
Channel area, A                        4.05 x [10.sup.-15] [m.sup.2]
Tube diameter, d                                    --
Chiral vector (n, m)                                --
Maximum electric field, [E.sub.m]               [E.sub.mSi]
Maximum current, [I.sub.d max]                 65.2 [micro]A
Carrier density, [I.sub.d max]/               0.8 [micro]A/nm
  (d or W)
DIBL                                            56.23 mV/V
Subthreshold swing, SS                         32.37 mV/dec
On-off ratio                                 3.8 x [10.sup.3]
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Title Annotation:Research Article
Author:Tan, Michael Loong Peng
Publication:Journal of Nanomaterials
Date:Jan 1, 2013
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