LSI DEBUTS HYDRA SERIALIZER/DESERIALIZER CORE.
"By leveraging our extensive experience in high speed SerDes technology, we're providing a highly flexible and configurable core that satisfies the requirements of a broad cross section of custom logic applications," said Jean Bou Farhat, vice president, CoreWare, LSI Logic. "Both our ASIC and RapidChip Platform ASIC customers will benefit from having a single SerDes that supports applications ranging from 155 Mb/s Sonet traffic to 3.125 Gb/s XAUI and CX4 interfaces."
Operating at 100 Mbps to 3.2 Gbps with in-system selectable LVDS and PCML I/O options, the Hydra core supports both 10-bit parallel interfaces (10 bits or 20 bits wide) and 8-bit parallel interfaces (8 bits or 16 bits wide). In addition, for a given speed of operation, the core operates with a wide range of reference clock frequencies. The core has full SerDes capability including clock and data recovery circuitry on the receiver to recover both clock and data from a received bit stream. Alternatively, the core may be configured to support source synchronous interfaces where a separate clock is sent with the data.
With this exceptional flexibility, the Hydra core supports a number of standards and data rates including, but not limited to Gigabit Ethernet, SGMII, XAUI, CX-4, Serial RIO, Parallel RIO, SFI4.1, SPI4.2, SPI5, and HyperTransport. The unique in-system selectable LVDS and PCML I/Os allow the design of single ports that support both LVDS-based and PCML-based interfaces such as SPI4.2 (LVDS) and XAUI (PCML). System and custom logic designers using the RapidChip Xtreme family of slices with the Hydra core can now meet the most demanding high I/O bandwidth specifications with unprecedented levels of functionality at an affordable price.
"With today's myriad of interface standards, SoC designers are looking for ways to quickly and efficiently implement compliant interfaces so that they can concentrate their efforts on meeting unique systems requirements that differentiate their end products," said Jerry Worchel, principal analyst, In-Stat/MDR. "By providing a single SerDes core that supports a broad range of interfaces in a configurable manner for both ASIC and RapidChip Platform ASIC designs, LSI Logic is extending the flexibility of its RapidChip slices while also providing designers with the capability to support multiple standards with a single interface port."
The LSI Logic CoreWare IP library provides the industry's most comprehensive set of IP solutions that are proven and designed to work seamlessly with the cell-based ASIC and RapidChip Platform ASIC design flows. CoreWare IP includes GigaBlaze and HyperPHY high-speed standards-compliant SerDes, high-performance ARM and MIPS processors and associated systems, licensable ZSP DSP cores, processor peripherals and AMBA on-chip-bus structures, USB cores, Memory PHYs and Controllers, Ethernet MAC and PHY cores, PCI Express, XGXS, SPI4.2 and other protocol layer IP. Customers can leverage CoreWare IP solutions to significantly reduce risk and turn-around times with complex SoC designs. Additionally, a dedicated worldwide IP support organization is available to assist customers in all aspects of CoreWare SoC design.
About LSI Logic Corporation
LSI Logic Corporation designs and produces high-performance semiconductors for Consumer, Communications and Storage applications that access, interconnect and store data, voice and video. LSI Logic serves its global OEM, channel and distribution customers with Platform ASICs, standard-cell ASICs, standard products, host bus adapters, RAID controllers and software. In addition, the company supplies storage network solutions for the enterprise. LSI Logic is headquartered at 1621 Barber Lane, Milpitas, CA 95035.
LSI Logic can be found on the World Wide Web at http://www.lsilogic.com/.
For more information, call 408/433-4245.
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|Date:||Dec 1, 2004|
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