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LATTICE TRIPLES ITS HIGH DENSITY PRODUCT LINE; RAISES INDUSTRY'S BAR ON SPEED, DENSITY AND TESTABILITY

 HILLSBORO, Ore., Oct. 11 /PRNewswire/ -- Lattice Semiconductor Corp. (NASDAQ: LSCC) today announced two new families of high-performance, high density programmable logic devices (HDPLDs), setting new standards for device speed, density and functionality. The six devices in the pLSI(R) and ispLSI(R) 2000 family boast the programmable logic industry's fastest devices with speeds up to 135 MHz, the only device family able to support new 66 MHz microprocessors including the Intel Pentium(TM). The six devices in the pLSI and ispLSI 3000 family feature unparalleled functionality with dedicated IEEE 1149.1 Boundary Scan capability and the industry's highest device densities of up to 14,000 gates. Together with the company's current high density pLSI and ispLSI 1000 family and its industry-leading high-performance GAL(R) devices, Lattice Semiconductor now offers the broadest, highest performance programmable logic product offerings from any supplier.
 "This introduction is significant on two fronts. We've focused the flexibility and performance strengths of our successful pLSI and ispLSI 1000 device architectures at the speed and density requirements of leading-edge communications and computing system design," stated Cyrus Tsui, president, chief executive officer and chairman of the board of Lattice Semiconductor. "Our new pLSI and ispLSI 2000 family has been optimized to offer the first high density device ever to meet the performance requirements of the industry's leading-edge commercial processors. The pLSI and ispLSI 3000 family, on the other hand, is the first commercially available high density PLD family to break through the 10,000 gate barrier in terms of logic density while supporting the industry's emerging system requirements for higher speed, boundary scan and in-system programmability."
 The ispLSI 1000, 2000 and 3000 devices feature the company's proprietary in-system programmability (isp(TM)). Lattice's isp technology enables on-board or in-system device reconfiguration and is the industry's only single chip, non-volatile solution.
 "As programmable logic devices continue their rapid ascent into higher densities and more sophisticated packaging techniques, in-circuit reprogrammability becomes increasingly critical," said Bob Beachler, senior analyst at Dataquest. "Without a mechanism to ensure lead conformance on fragile packages such as QFPs, the only avenue open to those wishing to accomplish in-house programming is through in-circuit programming techniques."
 "Analysts, users -- and most importantly, our customers -- have been saying all along that in-system programmability is becoming an increasingly critical capability for system prototyping and reconfiguration," said Steven Laub, vice president and general manager of Lattice Semiconductor. "By adding Boundary Scan and 135 MHz speed to our proprietary, non-volatile isp technology, we are well-positioned to continue our rapid penetration of the fast growing high density programmable logic market."
 Lattice Architecture
 Both the pLSI and ispLSI 2000 and pLSI and ispLSI 3000 families are based on Lattice's successful pLSI and ispLSI 1000 device architecture using the company's advanced E2CMOS(R) process for full reprogrammability. Each of the families feature the company's flexible Generic Logic Blocks (GLBs), proprietary Product Term Sharing Array (PTSA), multi-clocking support and deterministic routing. Within Lattice's GLB, the company's proprietary PTSA gives designers unprecedented flexibility by allowing full access of up to twenty product terms to each of the macrocells in a given logic block. Additionally, each of the device families has been designed with design portability in mind, allowing easy design density and performance migration between the families.
 The pLSI and ispLSI 1000, 2000 and 3000 families have each been optimized in performance, density and architecture to address specific applications. The pLSI and ispLSI 1000 family will continue to address the performance and density needs of interrupt, LAN, memory and DMA controllers; graphics subfunctions; data packet encoders and other glue logic applications.
 2000 Family: Industry's Fastest High Density Family
 The pLSI and ispLSI 2000 family of high density PLDs, boasting the industry's fastest performance, will target high-performance, speed- critical applications such as address decoders, small state machines, processor bus interfaces, counter/timers and glue logic. Device system performance extends up to 135 MHz (7.5 ns tpd) with densities up to 4,000 gates. The pLSI and ispLSI 2000 devices are offered in a variety of packages including the 44- and 84-pin PLCC, the 128-pin PQFP and the 100-pin, 1.4 millimeter thick TQFP for PCMCIA designs. The pLSI and ispLSI 2000 family provides an effortless migration path for high- performance, low-density PLD users who desire the integration benefits of high density without sacrificing device performance.
 3000 Family: Industry's Highest Density HDPLD Delivers Dedicated
 Boundary Scan
 "With our pLSI and ispLSI 3000 family devices, designers no longer need to make performance trade-offs to use a very high-density, feature- rich device," said Laub. "Today, boundary scan is becoming a key requirement for many system designs. Lattice is the only supplier to combine boundary scan and isp into a single non-volatile device. Lattice now offers the ultimate high density PLD for prototyping, system design and system test."
 The feature-rich pLSI and ispLSI 3000 family delivers functionality, flexibility and the industry's largest HDPLD at 14,000 gates. These six devices target high-performance, complex applications such as cache controllers, compression encoders, encryption/decryption and graphics functions. Device system performance extends up to 110 MHz (10 ns tpd) with densities from 8,000 to 14,000 gates. The pLSI and ispLSI 3000 devices are offered in a variety of packages including the 128-, 160- and 208-pin QFP, and the 167-pin PGA. With the industry's highest register count ranging from 288 to 480 registers, its innovative macrocell structure and IEEE 1149.1 Boundary Scan test standard on each part, the pLSI and ispLSI 3000 family sets the industry standard for flexibility, functionality and ease-of-use.
 Software Support
 The pLSI and ispLSI 1000, 2000 and 3000 families are supported by a broad range of proprietary and third-party tools for both PC and workstation platforms including the company's proprietary pDS design software package. Third-party tool support includes fitters for ABEL and Viewlogic on both PC and Sun workstation platforms. pDS support for the new device families is available now with ABEL and Viewlogic support scheduled for Q1 1994. Cadence Composer and Concept support is also planned for the first half of 1994.
 Pricing and Availability
 The pLSI 2032, ispLSI 2032, pLSI 3256, and ispLSI 3256 will be available in sample quantities by the end of 1993. The pLSI 2032 in a 44-pin PLCC package will be priced at $8.80 in 1,000 piece quantities. The pLSI 3256, in a 167-pin PGA package, will be priced at $175.00.
 Lattice Semiconductor Corp. is based in Hillsboro. The company designs, develops and markets both high and low density, high-speed E2CMOS programmable logic devices (PLDs). PLDs shorten design cycles and reduce development costs by allowing the customer to quickly and efficiently incorporate different logic functions on a single device. Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in the fields of microcomputers, computer peripherals, graphic systems, workstations, telecommunications, military systems and industrial controls. Company headquarters are located at 5510 N.E. Elam Young Parkway, Hillsboro, OR 97124-6421; Telephone, 503-681-0118; Fax, 503-681-3077; Telex, 277338 LSC UR.
 NOTE: The "2" in E2CMOS should be in superscript. E2CMOS, GAL, ispLSI, pDS, pDS+, pLSI and UltraMOS are registered trademarks of Lattice Semiconductor Corp. isp is a trademark of Lattice Semiconductor Corp.
 -0- 10/11/93
 /CONTACT: Stan Kopec of Lattice Semiconductor, 503-681-0118; or Marge Breya of KVO Public Relations, 503-221-1551, for Lattice Semiconductor/
 (LSCC)


CO: Lattice Semiconductor Corp. ST: Oregon IN: CPR SU: PDT

JH -- SE004 -- 0543 10/11/93 08:32 EDT
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Date:Oct 11, 1993
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