Printer Friendly

Articles from International Journal of Reconfigurable Computing (January 1, 2013)

1-10 out of 10 article(s)
Title Author Type Words
A heuristic scheduler for port-constrained floating-point pipelines. Jin, Zheming; Bakos, Jason D. 7062
An asynchronous FPGA block with its tech-mapping algorithm dedicated to security applications. Beyrouthy, Taha; Fesquet, Laurent 7096
An impulse-C hardware accelerator for packet classification based on fine/coarse grain optimization. Ahmed, O.; Areibi, S.; Collier, R.; Grewal, G. 13526
Analysis of fast radix-10 digit recurrence algorithms for fixed-point and floating-point dividers on FPGAs. Baesler, Malte; Voigt, Sven-Ole 12270
Design and implementation of an embedded NIOS II system for JPEG2000 Tier II encoding. McNichols, John M.; Balster, Eric J.; Turri, William F.; Hill, Kerry L. 5701
Fully pipelined implementation of tree-search algorithms for vector precoding. Barrenechea, Maitane; Mendicute, Mikel; Arruti, Egoitz 8115
Hardware accelerators targeting a novel group based packet classification algorithm. Ahmed, O.; Areibi, S.; Grewal, G. 14057
Rainbow: an operating system for software-hardware multitasking on dynamically partially reconfigurable FPGAs. Jozwik, Krzysztof; Honda, Shinya; Edahiro, Masato; Tomiyama, Hiroyuki; Takada, Hiroaki 28625
Runtime scheduling, allocation, and execution of real-time hardware tasks onto Xilinx FPGAs subject to fault occurrence. Iturbe, Xabier; Benkrid, Khaled; Hong, Chuan; Ebrahim, Ali; Arslan, Tughrul; Martinez, Imanol 18834
Transparent runtime migration of loop-based traces of processor instructions to reconfigurable processing units. Bispo, Joao; Paulino, Nuno; Cardoso, Joao M.P.; Ferreira, Joao Canas 14009

Terms of use | Privacy policy | Copyright © 2022 Farlex, Inc. | Feedback | For webmasters |