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Inphi Corporation's New 12.5 Gbps 1:8 Demultiplexer with Latched Comparator Input Enables High Frequency Communications and Computing Applications.

The Newest Member of Inphi's High Speed Logic Product Family Enables High Performance Communications and Computing Systems at the Industry's Highest Operating Frequencies.

WESTLAKE VILLAGE, Calif. -- Inphi[R] Corporation ( today announced the 1385DX, a 12.5 Gbps 1:8 Demultiplexer with Latched Comparator Input operating at bit rates from DC to 12.5 Gbps. Part of the High Speed Logic family of devices, the 1385DX, with its high sensitivity latched comparator input and auto-synchronizing demultiplexer, enables test and measurement, defense, and aerospace designers to develop high speed data acquisition front ends and to deserialize high speed signals.

"Validation of multi-gigabit serial interfaces in the next generation server memory architecture is difficult with extremely stringent performance and signal integrity requirements," said Levi Murray, Vice President, Technology Enabling and Infrastructure Development for Advanced Micro Devices. "Inphi has designed the 1385DX to enable us to properly characterize and validate these interfaces and to meet our performance and time-to-market objectives in a cost effective manner."

The 1385DX features a high-speed sampling clock and high-bandwidth latched comparator input that can be used to sample high-bandwidth analog signals and demultiplex them to a lower data rate for post-processing via a low speed FPGA or ASIC. Additionally, the high bandwidth input supports digital signals up to 12.5 Gbps, which are latched and deserialized to an eight bit parallel output bus. The 1:8 deserialization, coupled with an on-chip synchronization circuit and adjustable output levels, allow the use of multiple demultiplexers in parallel, with automatic alignment of the parallel output buses of the demultiplexers.

The 1385DX accepts a single external clock at up to 12.5 GHz that samples the input signal from the high-bandwidth comparator. Internally generated clocks are used for demultiplexing the latched input signal to an eight-bit parallel data bus. The device outputs a full-rate clock ( 1/8 of the input clock) or half-rate clock (1/16 of the input clock) as determined by the CLKSEL input.

The DEMUX's built-in synchronization circuit allows two or more 1385DXs to be automatically synchronized using a master/slave mode, in which the slave DEMUX synchronizes to a signal (CK16) from the master, or a slave/slave mode, in which both 1385DX's are synchronized to an external master clock (1/16 of the input clock frequency). Synchronization occurs within at most 152 periods of the input clock.

Key Features and Benefits:

The 12.5 Gbps 1:8 Demultiplexer with Latched Comparator Input operates from a standard +3.3 V power supply. It is currently shipping in pre-production quantities in an 8x8 mm QFN package or on an evaluation board with SMA connectors, and full production is expected to begin in Q1 2008. Information may be found at

About Inphi Corporation

Inphi Corporation designs and develops integrated circuits that consistently deliver the industry's highest performance and best signal integrity for processing high-speed digital data in computing and communications systems. The company is a leading supplier of memory interface logic, optical components and High Speed Logic that deliver the world's highest performance as measured by signal integrity. Leading corporations rely on Inphi for components that transport, store, deliver, and test high-speed data for the world's most innovative high-performance communications and computing systems. Inphi is recognized as a global technology leader for its innovative designs, dedication to the development of open standards, and excellence in R&D. Learn more about Inphi Corporation, by visiting
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Publication:Business Wire
Date:Jan 8, 2008
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