Printer Friendly

InnoLogic Systems' Equivalence Checker Improves Verification of Critical Elements Within Full Custom Silicon Designs.

Business/Technology Editors

SAN JOSE, Calif.--(BUSINESS WIRE)--May 6, 2002

InnoLogic's ESP-CV Improves Coverage and Reduces Run-Times

for Sun Microsystems, nVIDIA and VIA Technologies

InnoLogic Systems, Inc. a leading provider of formal verification solutions for full custom silicon design implementations today announced that it has received major customer endorsements from VIA Technologies, nVIDIA and Sun Microsystems. All three companies used InnoLogic Systems' ESP-CV equivalence checker to verify and debug specific, critical elements within their designs. With ESP-CV, the three companies achieved higher functional coverage and reduced the amount of time required to verify certain elements within their designs including multi-million transistor memory blocks. .ESP-CV verifies that two different design representations, such as Verilog behavioral models and transistor level views, are functionally equivalent. When differences are found, ESP-CV produces a set of binary vectors that can then be used for debug.

Dian Yang, CEO and president of InnoLogic noted, "We are pleased to receive these significant customer endorsements from major product developers for our ESP-CV product. These endorsements provide further evidence of the demand that we are seeing for our products which, in revenues, translates to $1-million per quarter. This announcement, in conjunction with the introduction today of Rev 5.0 of our ESP-CV product (See Press Release, "InnoLogic Systems Introduces Rev 5.0 of ESP-CV Equivalence Checker," dated May 6, 2002) validates the unique value proposition of our formal verification products for full custom silicon designs."

"Full custom silicon implementations contain certain design elements that are very difficult to formally verify with mainstream tools" continued Yang. "For example, the full custom logic blocks and embedded memories that are characteristic elements within high performance SOCs can cause conventional verification tools to bog down and perform very inefficiently. ESP-CV proactively and effectively addresses these design elements to provide designers with an extra level of confidence that the finished full custom silicon will perform as originally specified."

Sun Microsystems Inc. used ESP-CV to verify the 1MB Level 2 cache in a multi-million gate processor design. Sridhar Narayanan, design technologies manager, Processor Products Group, Sun Microsystems stated, "ESP-CV has proven to be extremely useful in our design flows. The ability to efficiently debug problems while minimizing total runtimes for complete verification has been vital to creating a high-quality design that meets our product schedules."

nVIDIA, one of InnoLogic's first customers, most recently used ESP-CV in the verification of a 60-million-transistor GeForce3 GPU. Chris Malachowsky co-founder and vice president of engineering said, "We found ESP-CV to be effective and easy to use. ESP-CV finds any discrepancy between transistor and behavioral level models thereby closing the loop between the circuit designers and the SOC design team."

VIA Technologies used ESP-CV to verify content addressable memories (CAMs) contained in PC and graphics chipsets. Alan Liaw, director of VIA's R&D division said, "Complex embedded memories are essential for competitive processor products. ESP-CV enables us to enhance our verification methodology by dramatically increasing coverage and reducing verification time. Our satisfaction with ESP-CV is such that we are incorporating it as a permanent step within our embedded memory design flow."

About ESP-CV

InnoLogic Systems' ESP-CV toolset, which incorporates InnoLogic's patented symbolic simulation technology, verifies that two different design representations are functionally equivalent. These representations may be in the form of Verilog behavioral models, RTL, UDPs, gate, transistor level or SPICE netlist views. If a difference is found during the equivalence check process, ESP-CV produces a shallow set of binary vectors that depict the difference. These vectors can then be used in the debug process to determine the root cause of the difference.

About InnoLogic Systems, Inc.

InnoLogic Systems, Inc. is the leading EDA provider of formal verification solutions for full custom silicon implementations. The company's patented symbolic simulation technology, currently in production use by leading full custom designers, combines the power of formal verification methods with event-driven simulation technology. These toolsets are designed to complete mainstream verification solutions by providing higher functional coverage and faster verification of full custom logic blocks contained within high performance SOC designs. The San Jose-based company has customers in Europe, the U.S., Japan and Taiwan in major market segments including networking, processors and memory. Additional information about InnoLogic Systems can be found at www.innologic-systems.com or by calling 408-432-6188.

Note to Editors: InnoLogic is a trademark of InnoLogic Systems, Inc. All other brand or product names may be trademarks or registered trademarks of their respective companies and should be treated as such.
COPYRIGHT 2002 Business Wire
No portion of this article can be reproduced without the express written permission from the copyright holder.
Copyright 2002, Gale Group. All rights reserved. Gale Group is a Thomson Corporation Company.

Article Details
Printer friendly Cite/link Email Feedback
Publication:Business Wire
Date:May 6, 2002
Words:741
Previous Article:Pearson Education and Connextions.net Team to Develop an Innovative Multi-Channel, Multi-Lingual Customer Service Solution.
Next Article:IBM and Open Solutions To Market Integrated Banking Solutions to Community Based Financial Institutions.


Related Articles
SUN Microsystems Purchases InnoLogic Systems' Custom Equivalence Checker for Systems-on-a-Chip Design Projects.
AGILENT'S NETWORKING AND COMPUTING GROUP INCORPORATES VERPLEX FORMAL VERIFICATION SOLUTION IN DESIGN FLOW.
NEC CORPORATION STANDARDIZES ON VERPLEX FORMAL VERIFICATION TOOLS.
InnoLogic Systems Introduces Rev 5.0 of ESP-CV Equivalence Checker; InnoLogic CKT enables formal verification at the circuit level; COV feature...
Sunplus selects Verplex to verify all chip designs.
Virage Logic Uses InnoLogic Systems' Tools for Functional Verification of Its ASAP Memory Product Line.
InnoLogic Systems Tools Validate Functional Models for STMicroelectronics Embedded Memories.
InnoLogic Systems Joins Novas' Harmony Program to Deliver Comprehensive Verification Offerings to SoC Designers.
InnoLogic Systems Tools Cited as Important in Helping Fujitsu Meet Production Delivery of Recently Announced Mobile FCRAM.
Synopsys Acquires InnoLogic Systems, Inc.

Terms of use | Privacy policy | Copyright © 2018 Farlex, Inc. | Feedback | For webmasters