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In case you missed it.

Conformal Coatings

"Parylene as a Suppressant for Tin Whiskers Growth on Printed Circuit Boards"

Author: Rakesh Kumar, Ph.D.; rkumar@scscoatings.com

Abstract: Numerous studies identified several strategies to mitigate tin whisker risks until a method is found to completely eliminate the problem. One mitigation strategy is conformal coating application. This paper reviews various options and presents a practical solution using Parylene coating technology for suppressing formation of metallic whiskers, OSEs and dendrites. It has been observed that Parylene conformal coatings are more suitable for suppressing metallic whiskers than other conformal coatings or other proposed solutions. (Apex, February 2007.)

Pb-Free Rework

"The New Lead-Free Assembly Rework Solution Using Low Melting Alloys"

Authors: Polina Snugovsky, Ph.D., S. Bagheri, Z. Bagheri and M. Romansky; polina@celestica.com

Abstract: This paper describes a new Pb-free SMT rework process that avoids component overheating, reduces board warpage and cratering, and prevents adjacent components from thermal damage. A solder alloy with a melting range lower than SnAgCu solder is used to replace a BGA on an organic substrate. The Pb-free solder pastes analyzed include two indium-containing alloys, melting range 181-187[degrees]C and 138[degrees]C, respectively, and a bismuth-containing alloy, melting range 195[degrees]-209[degrees]C. In this work, CBGA937, PBGA196 and CSP46 components with SAC405 balls were assembled using SAC405 solder. Then, rework was performed with three compositions of low-melt solders using different profiles.

The microstructures of mixed solder joints were analyzed using optical and scanning electron microscopy methods. Two solder pastes and rework profiles were chosen for thermal cycling. A limited ATC study was done in a temperature range of 0-100[degrees]C. It was observed that fatigue life was component-dependent, and when fully mixed, solder joints had better or equal reliability to that of the pure SAC405 assemblies. (Apex, February 2007.)

Surface Finishes

"Effect of OSP Chemistry on the Hole Fill Performance During Pb-Free Wave Soldering"

Authors: Bala Nandagopal, Sue Teng and Doug Watson; sue.teng@cisco.com

Abstract: This paper analyzes the differences in plated through-hole fill performance between the regular OSP and Pb-free OSP PCB surface finish chemistries in a Pb-free wave solder process. Variables studied include two board thicknesses (0.093" and 0.125"), three hole sizes (pin plus 0.016", 0.024" and 0.040"), internal copper layer connections (single and three plane layer connections), two pin shapes (circular and rectangular), and two reflow atmospheric preconditions (nitrogen and air). The bare PCBs were initially subjected to 220[degrees] and 240[degrees]C peak reflow process twice for the SnPb and Pb-free wave soldering samples, respectively. Pb-free wave soldering results indicated that the Pb-free OSP performed better than the regular OSP chemistry by 15% under air and 40% under nitrogen reflow preconditioning. In Pb-free wave soldering, the air preconditioning resulted in better hole fill than nitrogen. Board-to-board variation of hole fill was much lower in the Pb-free OSP chemistry compared to regular OSP. PTH sizes of 0.040" and 0.016" larger than the pin diameter proved to be best and worst designs, respectively, for the 0.125" PCB. The SnPb control almost had greater than 92% average hole fill for every design variable in this experiment. Overall, the results indicated that the regular OSP chemistry in Pb-free wave soldering failed to meet the 50% hole fill required per IPC-A-610, for all the conditions studied. The 0.125"-thick PCB using Pb-free OSP chemistry also failed to meet the IPC requirements for all conditions evaluated. However, the 0.093"-thick PCB using Pb-free OSP chemistry was able to meet this 50% hole fill requirement (although not meeting the general 75% minimum requirement), except when the hole diameter is 0.016" larger than the pin. (Apex, February 2007.)

Test and Inspection

"Improving SMT Yield with AOI and AXI Test Results Analysis"

Authors: An Qi Zhao, Xin Yong Yu, Li Ming Gong, Zhen (Jane) Feng, Ph.D., Mark Evans and Murad Kurwa; jane.feng@flextronics.com

Abstract: This study started with one customer's product, which previously had 100% components covered with AOI and >95% covered by AXI. AOI, AXI, ICT and functional test data were studied for six months, and AXI test coverage reduced for some noncritical components. As a result of the reduction of AXI coverage, AXI test time was reduced to below three minutes from above four minutes. Also investigated were process issues and improvements using daily AOI and AXI test results. An example of one product: AXI test time was reduced by testing only BGAs, fine pitch ICs, RNs and some "critical to function" parts. Therefore, AXI component and pin coverage changed from 98.4% and 98.9% to 13.6% and 50.1%, respectively. AXI test time was reduced to 2 minutes from 4.1 minutes. Meanwhile, the yields of AOI (top), AOI (bottom), AXI, ICT, and FT increased from 98.9%, 97.3%, 88.4%, 98.9% and 100% to 99.6%, 99.0%, 96.2%, 98.9% and 100%, respectively. Cost savings are also discussed. (Apex, February 2007.)

CIRCUITS ASSEMBLY provides abstracts of papers from recent industry conferences and company white papers. With the amount of information increasing, our goal is to provide an added opportunity for readers to keep abreast of technology and business trends.
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Article Details
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Title Annotation:Technical Abstracts
Publication:Circuits Assembly
Date:May 1, 2007
Words:873
Previous Article:High-end PCB CAD.
Next Article:More Groves, not Graves.


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