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"PCB Design and Assembly Process Development of 01005 Components with Lead Free Solder"

Authors: Yueli Liu, Shaunte Rodgers and Dr. R. Wayne Johnson;

Abstract: Chip components in 01005 dimensions are commercially available. However, the implementation of such tiny components into new products presents design and assembly process challenges. In this study, a test vehicle was designed to investigate the effect of PCB pad design on assembly yield. Process capability of 01005 test board manufacturing was evaluated. A DoE was used to optimize the solder paste printing based on 3-D solder paste inspection. Pb-free solder was used for all assembly trials. Several tests were performed to explore the influences of process parameters on placement accuracy and reflow defects. Through analysis of experimental results and post-reflow inspection for assembly defects, recommendations for PCB design and assembly processes are made. (IPC Apex, February 2006)

Process Optimization

"0201 Process and Yield Improvement During Launch to Production"

Author: Jason Fullerton;

Abstract: This paper focuses on the optimizations performed on a particular assembly installed in a small form factor barcode scan engine. The PCB as processed during SMT assembly is a 96-up panel with overall dimensions of 279.4 x 279.4 x 0.79 mm on standard FR-4 laminate. Each individual image is 24.50 x 14.25 mm and incorporates double-sided assembly on a four-layer circuit design. In addition, a test PCB assembly exists that has a 10 x 10 array of 0201 components on both sides, and [micro]mBGA components on the second pass assembly side. This PCB is a single image design, with overall dimensions of 279.4 x 279.4 x 1.58 mm, on standard FR-4 material with four internal copper layers. Aspects such as land layout, surface finish, solder stencil apertures, stencil materials and fabrication processes are considered, as are board support methods and strategies, handling and placement. (IPC Apex, February 2006)

"Surviving the 'Green' Heat Wave"

Authors: Mike Olla and Steven Daigle;

Abstract: Many component manufacturers and end-users are finding it necessary to verify the reliability and survivability of the wide variety of components at higher temperatures required by Pb-free solder. Using commercial IR reflow ovens to statistically profile Pb-free parts to Jedec, IPC, JAPAN and other high-temperature reflow specifications has been difficult. The difficulty is achieving accurate and repeatable temperature ramp rates of 6[degrees]C/sec. or higher with little to no overshoot at the peak of the reflow cycle, which is critical in evaluating device integrity. This paper addresses how a novel oven verifies "green" packages and provides meaningful data. The oven is a repeatable, real-time data logging, seven-zone oven that is programmable to produce ramp rates from 1[degrees] to 20[degrees]C/sec. with no overshoot and control temperatures up to 400[degrees]C [+ or -]2[degrees]C in an [N.sub.2] environment to minimize lead oxidation. The profile oven has the capability of real-time electrical testing during the profile time using up to 20 I/O signals. A temperature sample is collected every two seconds and displayed. Covered are problems of using conventional profiling techniques and why more accurate temperature profiling is necessary to guarantee reliable, long-term device performance. (IPC-Jedec Pb-Free Conference, December 2005)


"Predicting Plated Through Hole Life at Assembly and in the Field from Thermal Stress Data"

Authors: Michael Freda and Dr. Donald Barker;

Abstract: Over the past 10 years, two new test methods--Interconnect Stress Test and Highly Accelerated Thermal Shock--have been developed to perform thermal cycling testing and, in particular, to measure plated through-hole reliability. Both methods have proved useful in their ability to quantify plated through-hole reliability and have gained a wide level of acceptance and creditability within the industry. Along with more traditional air-to-air and liquid-to-liquid thermal cycle methods, the two tests expand the test methods available to the interconnect industry. While the number of testing options for PTH thermal cycling has increased, little work has been performed within the industry on developing methods to analyze and use the data coming from these new test methods. This paper covers use of IST testing to obtain PTH cycle-to-failure data followed by methods to analyze and plot the data over a range of temperatures. In particular, the paper focuses on the use of material properties like the modulus as a function of temperature and CTE as a function of temperature to calculate the stress on a PTH hole versus temperature. Also explored: the use of the Inverse Power Law to analyze the PTH stress versus cycle to failure relationship. Once IPL has been used to establish the cycle-to-failure relationship to stress for a given laminate and PCB design, it is then possible to estimate the number of cycles to failure in the field as a function of the number of cycles of assembly stress, the peak assembly temperature and the maximum temperature in the field. (IPC Apex, February 2006)

CIRCUITS ASSEMBLY provides abstracts of papers from recent industry conferences and company white papers. With the amount of information increasing, our goal is to provide an added opportunity for readers to keep abreast of technology and business trends.
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Title Annotation:Technical Abstracts
Publication:Circuits Assembly
Date:Apr 1, 2006
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