Improvement in brightness uniformity by compensating for the threshold voltages of both the driving thin-film transistor and the organic light-emitting diode for active-matrix organic light-emitting diode displays.
The most critical advantage of organic light-emitting diode (OLED) displays over conventional liquid crystal displays (LCD) is that OLED displays do not require backlight module systems. OLED displays can exhibit high contrast, wide viewing angle, fast response time, and low power consumption. Moreover, OLED panels can be thinner and lighter than LCD panels [1-3]. OLED displays are currently designed to use passive-matrix (PM) or active-matrix (AM) modes. PMOLED displays use a grid to supply charges to a pixel, and AM-OLED displays use low-temperature polycrystallinesilicon thin-film transistors (LTPS-TFTs) to provide a driving current. AM-OLED displays are becoming increasingly popular because they provide more favorable high image contrast and performance than PM-OLED displays do . Moreover, AM-OLEDs have the advantage of using less driving current compared with PM-OLEDs, which can increase the lifetime of OLED materials .
AM-OLEDs differ from LCDs because the value of the current flowing through the lighting element controls the luminance of each lighting element; that is, AM-OLEDs use current-controlled lighting elements. Thus, the brightness of an OLED is proportional to the amount of current passing through the diode. To obtain a uniform distribution of brightness, AM-OLED displays must uniformly deliver current to the OLED. However, the inevitable variation in the excimer laser annealing (ELA) process, which is used to form the poly-Si channel, causes a wide variety of electrical characteristics in individual LTPS-TFTs, resulting in a nonuniform driving current . Furthermore, electrical performance degradation of AM-OLEDs caused by long-term operation decreases their brightness, which can be the threshold voltage degradation of driving TFTs (DTFTs) and OLEDs in a pixel circuit [5, 6]. The voltage drop across the parasitic resistance of a power line, called I x R (current x resistance) drop voltage, also causes nonuniform brightness in AM-OLED panels . These differences in the threshold voltages of DTFTs and OLEDs and the I x R drop voltage of a power line cause different currents flowing into the OLED among the pixels. Tightening the threshold voltage variation and preventing the luminance degradation of OLEDs are very crucial to AM-OLED technology. It is reported that the two-TFT and one-capacitor (2T1C) pixel circuit suffers from pixel-to-pixel luminance nonuniformity because of the threshold voltage variation of DTFTs (shown in Figure 1). This issue is exacerbated as the size of a display increases. Instead of improving TFT processes, several studies have attempted to reduce the brightness variation across display panels by altering pixel circuit designs, which can use voltage driving, current driving, and digital driving compensation approaches [8-15]. The current driving method can minimize the shift in the DTFT threshold voltage; however, it requires a longer pixel charging time than that of voltage driving method because of the high parasitic capacitance of a data line. The digital compensation has two methods, such as area ratio grayscale method and time ratio grayscale method. These two methods have an advantage that OLED current can be partly uniform against the variation of the DTFT characteristic. However, the grayscale numbers of area ratio grayscale method and time ratio grayscale method are limited by the subarea number and the subframe number, respectively. Nowadays, the grayscale of display has already become a huge amount, so the digital methods were not suitable for application on the high resolution for AMOLED . The voltage driving method can effectively manage the threshold voltage shift and also solve the nonuniform brightness problem. However, most studies have not simultaneously compensated for the threshold voltage variation of DTFTs and OLEDs and the I x R drop voltage [8-15].
This paper proposes a novel voltage programming AMOLED pixel circuit to produce displays with uniform brightness. The proposed pixel circuit, which comprises five n-type LTPS-TFTs and one capacitor, can compensate for the nonuniformity of OLED currents caused by the threshold voltage variations of DTFTs and OLEDs. The pixel circuit can also simultaneously compensate for the OLED luminance degradation caused by the IxR drop voltage of a power line. The simulation results indicated that the proposed pixel circuit successfully supplies a highly stable OLED current and is suitable for larger AM-OLED displays.
2. Operation of the New Proposed Voltage Programming Pixel Circuit
To achieve a stable OLED current even through the DTFTs and OLEDs producing threshold voltage variations, a five-TFT and one-capacitor pixel circuit was designed. Figure 2(a) shows a schematic of the proposed pixel circuit, which includes one DTFT, four switching TfTs (Sw1 to Sw4), one storage capacitor ([C.sub.ST]), one OLED, and three signal lines ([V.sub.SCAN1], [V.sub.SCAN2], and [V.sub.DATA]). Sw1 is used to turn the DTFT into a diode-connected structure; Sw2 detects the voltage between the gate and the drain ([V.sub.GD]) in the DTFT; Sw3 controls the emission stage of the OLED; Sw4 is used to control data input. [V.sub.SCAN1] and [V.sub.SCAN2] are the control signals used to turn the switching TFTs (Sw1 to Sw4) on or off. VDATA represents a data-voltage signal and VDD refers to a constant-voltage source. The control-signal timing diagram for the proposed circuit is divided into three stages, as shown in Figure 2(b). The three circuit operations stages are Periods (1), (2), and (3), which refer to a reset period, a compensation period with data input, and an emission period, respectively. The equivalent circuits at each operation stage are shown in Figure 3. The operational method and compensation principle that apply to the proposed pixel circuit are described as follows.
2.1. Reset Period. The functions in this stage are precharging and resetting the voltage stored in CST. [V.sub.SCAN1] and [V.sub.SCAN2] are high and [V.sub.DATA] is low; therefore, Sw1, Sw2, Sw3, and Sw4 are turned on. The voltage located at Node A is charged to [V.sub.RESET] through Sw1 and Sw2. The voltage previously stored in [C.sub.ST] is reset; therefore, the gate voltage of the DTFT connected to [C.sub.ST] is also reset for initialization. This stage can be used to reset gate voltage of DTFT which is composed of the [V.sub.DATA] and the compensated voltage in the previous emission period. In addition, the charging current will flow through the OLED in the reset period to cause the decreased contrast ratio except that extra scan lines for switch TFTs are added in the circuit [11,16].
2.2. Compensation Period with Data Input. In this stage, the threshold voltage of the DTFT ([V.sub.TH]) is detected by the compensation operation. When [V.sub.SCAN1] returns to a low value, Sw2 and Sw3 are turned off. When [V.sub.SCAN2] remains high, Sw1 and Sw4 stay on. At this moment, when a data voltage ([V.sub.DATA]) is applied, the voltage at the source electrode of DTFT becomes [V.sub.DATA] and the gate electrode of DTFT is charged to a higher potential, which is sufficiently high not to interfere with the compensation operation at this stage. Hence, the gate voltage of DTFT ([V.sub.A]) is discharged through Sw1, DTFT, and Sw4 until the DTFT is turned off. The gate voltage of DTFT that has a diode-connect structure reaches [V.sub.DATA]+ [V.sub.TH], where [V.sub.TH] is the DTFT threshold voltage. Because Node B is set to ground, the voltage across [C.sub.ST] can be written as [[V.sub.A] - [V.sub.B] = [V.sub.DATA] + [V.sub.TH].
2.3. Emission Period. During the emission stage, when [V.sub.SCAN1] becomes high, this turns on Sw2 and Sw3. [V.sub.SCAN2] then returns to a low value, Sw1 and Sw4 are turned off, and [V.sub.DATA] also decreases to a low value. Capacitor [C.sub.ST] maintains the gate voltage of DTFT ([V.sub.DATA] + [V.sub.TH]) until the reset stage of next operation cycle. The OLED current ([I.sub.OLED]), which equals the drain current of DTFT in the saturation region, can be written as
[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] (1)
[K.sub.DTFT] = [mu][c.sub.ox] W/L. (2)
Thus, [I.sub.OLED] is independent of the DTFT and OLED threshold voltages and is only affected by the data voltage ([V.sub.DATA]). The proposed pixel circuit effectively compensates for both the DTFT and OLED threshold voltage shifts and improves the display image quality for AM-OLED displays.
3. Simulation Result and Discussion
AIM-SPICE was used to simulate the proposed pixel circuit to investigate the compensation capability of the threshold voltage shifts of DTFTs and OLEDs. The AIM-SPICE poly-Si TFT model, poly-Si TFT model PSIA2 (level 16), was used in the simulation. The OLED was modeled using a diode-connected poly-Si TFT and a capacitor. Table 1 shows the simulation parameters. The simulated I-V curves of the poly-Si TFT (DTFT) and OLED with the parameters of Table 1 are shown in Figures 4(a) and 4(b), respectively.
Figure 5 shows the transient waveforms of each DTFT node when the data voltage ([V.sub.DATA]) is 3 V. At the compensation stage with data input (Period (2)), the DTFT gate voltage is discharged to [V.sub.DATA] + [V.sub.TH] = 4 V, where [V.sub.TH] is the DTFT threshold voltage. During the emission stage (Period (3)), the DTFT gate voltage is maintained at 4 V ([V.sub.DATA] + [V.sub.TH]) as the DTFT [V.sub.GS]. Thus, the proposed circuit successfully compensates for the threshold voltage degradation of DTFTs and OLEDs. Figure 6 shows the simulated transient results obtained by varying the DTFT threshold voltage ([DELTA][V.sub.TH] = -0.33, 0, and + 0.33 V). The OLED cathode voltage was insensitive to the DTFT threshold voltage deviation. The error rates of the OLED cathode voltage when [DELTA][V.sub.TH] = 0 and [+ or -] 0.33 V were all below 0.03%. Therefore, the current flowing through the OLED was uniform. Thus, the proposed pixel circuit reduced the effect of DTFT and OLED threshold voltage deviations.
The OLED driving current affects the OLED luminance and represents the display brightness. The simulation results indicated that the DTFT threshold voltage deviation caused the OLED current variation. The error rate of the OLED current [I.sub.OLED]) is defined as the difference between the shifted OLED driving current ([DELTA][V.sub.TH] = [+ or -] 0.33 V) and the normal OLED current ([DELTA][V.sub.TH] = 0 V), as shown in the following equation:
= [I.sub.OLED] ([DELTA][V.sub.TH] = [+ or -]0.33 V) - [I.sub.OLED] ([DELTA][V.sub.TH] = 0 V)/[I.sub.OLED] ([DELTA][V.sub.TH] = 0 V). (3)
Figures 7(a) and 7(b) present the OLED currents ([I.sub.OLED]) and their error rates when [DELTA][V.sub.TH] = [+ or -] 0.33 V at various data voltage, respectively. The figures clearly indicate that the average [DELTA][V.sub.TH] error rate is below 0.8% for the proposed circuit. The average error rates of conventional 2T1C and other published pixel circuits are approximately 30% and 5%, respectively [10-12]. Therefore, the display image quality of panels that use the proposed pixel circuit will be more uniform than conventional 2T1C and reported pixel circuits.
Figure 8 presents the simulation results of the [I.sub.OLED] degradation rates of the proposed circuit and the conventional 2T1C pixel circuit when the range of the I x R drop voltage of a power line ([DELTA][V.sub.DD]) is 0.5 V. The initial VDD value was set to 12 V and the I x R drop voltage ([DELTA][V.sub.DD]) was set to 0.5 V; that is, the [V.sub.DD] decayed from 12 V to 11.5 V. In conventional 2T1C pixel circuit, the [I.sub.OLED] degradation rate is approximately 70% to 80%. The proposed pixel circuit can improve the [I.sub.OLED] degradation rate caused by the I x R drop voltage of a powerline. In addition, the [I.sub.OLED] degradation rate when [DELTA][V.sub.DD] was 0.3 V improved to approximately 5.8%. This demonstrates that the proposed pixel circuit can effectively solve the issue of I x R drop voltage.
Figures 9(a) and 9(b) present the [I.sub.OLED] value and its error rate when the degradation of the OLED threshold voltage ([DELTA][V.sub.TH_OLED) is +0.33 V at a range of data voltages between 1V and 4.5 V, respectively. After long-term operation, the OLED threshold voltage ([V.sub.TH_OLED]) increases, causing the brightness and quality of the display to deteriorate. As shown in Figure 9(b), the proposed pixel circuit can compensate for OLED degradation and the average ZOLED error rate was 4.7%. Therefore, the display image uniformity improved as a result of the decreased [I.sub.OLED] error rate.
This study proposed a voltage programming pixel circuit for AM-OLED displays and verified the circuit using the AIMSPICE simulator. The proposed circuit was composed of five TFTs and one capacitor and it simultaneously compensated for the threshold voltage variations of DTFTs and OLEDs and the I x R drop voltage of a power line. The simulation results demonstrated that the average error rates of the OLED current when [DELTA][V.sub.TH] = [+ or -]0.33 V for DTFTs and [DELTA][V.sub.TH_OLED] = +0.33 V for the OLEDs were less than 1% and 5%, respectively. The average error rate was also less sensitive to the 1 x drop voltage of a power line. Therefore, the proposed circuit exhibited high immunity to the threshold voltage deviation of both DTFTs and OLEDs and improved the brightness uniformity of AM-OLED displays.
Conflict of Interests
The authors declare that there is no conflict of interests regarding the publication of this paper.
The authors would like to acknowledge the financial support of the National Science Council of Taiwan under Contract nos. NSC 101-2221-E-011-070 and NSC 102-2221-E-011-112MY2 and of the Taiwan Building Technology Center (TBTC) of National Taiwan University of Science and Technology (NTUST).
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Ching-Lin Fan, (1,2) Hao-Wei Chen, (2) Hui-Lung Lai, (1) Bo-Liang Guo, (1) and Bohr-Ran Huang (1,2)
(1) Department of Electronic and Computer Engineering, National Taiwan University of Science and Technology, Taipei 106, Taiwan
(2) Graduate Institute of Electro-Optical Engineering, National Taiwan University of Science and Technology, Taipei 106, Taiwan
Correspondence should be addressed to Ching-Lin Fan; email@example.com
Received 14 February 2014; Revised 18 April 2014; Accepted 29 April 2014; Published 24 June 2014
Academic Editor: Liang-Sheng Liao
TABLE 1: Simulation parameters of the proposed pixel circuit. Devices W/L (Sw1~Sw4) ([micro]m) 8/2 [V.sub.TH] 1 (DTFT) (V) W/L (DTFT) ([micro]m) 12/2 [V.sub.TH_OLED] 1 (OLED) (V) Cst (pF) 0.35 [C.sub.OLED] (pF) 1 [[mu].sub.FET] 51.48 51.48 ([cm.sup.2]/Vs) Signal line [V.sub.SCAN1] (V) -3 to 15 [V.sub.DATA (v) 1 to 4.5 [V.sub.SCAN2] (V) -3 to 15 [V.sub.DD] (V) 12
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|Title Annotation:||Research Article|
|Author:||Fan, Ching-Lin; Chen, Hao-Wei; Lai, Hui-Lung; Guo, Bo-Liang; Huang, Bohr-Ran|
|Publication:||International Journal of Photoenergy|
|Date:||Jan 1, 2014|
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