Printer Friendly

Implementation of a memcapacitor emulator with off-the-shelf devices.


The discovery of the physical model of a memristor by the HP group [1] has attracted considerable interest from researchers in the areas of memory, neural synapses and logic circuit applications [2]-[6]. The model was originally postulated by Leon O. Chua as the fourth basic circuit element [7]. Related two other circuit elements, memcapacitors and meminductors [8], which are the higher-order elements in Chua's [alpha] and [beta] periodic table [9], also show memory features. Though it is widely known that memristors, memcapacitors and meminductors are promising elements for the implementation of memory smaller than any other existing memories, they are not expected to be commercially available in the near future due to cost and technical difficulties. Emulators can be useful alternatives for the development of application circuits.

In contrast to memristor emulator [10], memcapacitor emulator has not been studied actively so far. The only contribution for memcapacitor emulator is a mutator-based approach, in which memcapacitance is obtained via transforming memristance using mutators [11]-[13]. Since the memcapacitor is built in an indirect way of employing mutators, the circuit is rather complicated, which leads to difficulty in building complicated circuits. Recently, Biolek et al., presented a SPICE model of the memcapacitor emulator without a mutator [14]. However, it is only a SPICE model, and its feasibility has not yet been proven. In this study, we designed a simple dedicated memcapacitor circuit without mutators and implemented it with off-the-shelf electronic devices. It is the first memcapacitor emulator implemented with commercially available devices. The operation of the proposed memcapacitor emulator as a memcapacitor has been shown via both breadboard experiments and PSPICE circuit simulations.


Memcapacitance is based on the nonlinear relationship between integral of charge and integral of flux. Memcapacitor with a relation [f.sub.MC] ([sigma], [phi]) is defined as


Assume that [phi] is a function of [sigma], then, it leads to

d[phi]/dt = [d[phi]/d[sigma]] [d[sigma]/dt]. (2)

Since d[phi]/dt = v(t) and d[sigma]/dt = q(t), it follows from (1) and

(2) that

v(t) = [d[phi]/d[sigma]] q(t), or q(t) = [d[sigma]/d[phi]] v(t). (3)

Therefore, the term [d[sigma]/d[phi]] in (3) denotes a kind of capacitance with nonlinear features called memcapacitance and is denoted as

[C.sub.M] = d[sigma]/d[phi]. (4)

By applying a voltage or current to the memcapacitor, its capacitance can be altered. A common fingerprint of the memcapacitor and the memcapacitive system is their pinched hysteresis loops in the charge versus voltage plane, under any bipolar sine wave-like excitations, which is the unique qualitative phenomena that are absent from that of other passive elements resistor, inductor, and capacitor. Due to these phenomena, the capacitance depends upon the past history of input signal, which enables this device to function as a memory.

The voltage controlled memcapacitor is defined as

q(t) = [C.sub.M] ([x.sub.1], [x.sub.2], ..., [x.sub.n]) v(t), (5)

where [C.sub.M] is the memcapacitance and [x.sub.i]'s are the state variables and q and v are charge and voltage respectively. The state variables [x.sub.1], [x.sub.2], ... [x.sub.n] are defined by "n" differential equations where n [greater than or equal to] 1, called the associated state equations, as follows

[dx/dt] = f [x, x, ..., x, v], k = 1,2 ... n. (6)

If the device possesses only a single variable x (n = 1) and it is a function of only the voltage v, the device is called ideal voltage controlled memcapacitor.

Similarly the nth order charge controlled memcapacitive system is defined as:

v(t) = [D.sub.M] ([x.sub.1], [x.sub.2], ..., [x.sub.n])q(t), (7)

[dx.sub.k]/dt = [f.sub.k] [[x.sub.1], [x.sub.2], ..., [x.sub.n],q], k = 1,2 ... n, (8)

where [D.sub.M] is the inverse of memcapacitance [C.sub.M.sup.-1].

The basic relation between v(t), q(t), and internal state x(t) for n = 1 in a charge-controlled memcapacitor is defined as:

v(t) = [D.sub.M] (x, q, t)q(t), (9)

dx(t)/dt = f (x, q, t), (10)

where [D.sub.M]() and f() are the nonlinear functions that depend on the physical implementation of the memcapacitive systems.

Figure 1 shows the concept of a memcapacitor in which the capacitance is adjusted by the width (L) of the dielectric [14]. L is varied from [L.sub.min] to [L.sub.max] according to the limits of capacitances ([C.sub.M,max], [C.sub.M,min]) and inverse capacitance ([D.sub.M,min], [D.sub.M,max]).

The inverse of the memcapacitance that depends on the state variable is given by

[D.sub.M](t) = [D.sub.M,Min] + [DELTA]Dx(t), (11)

where [DELTA]D = ([D.sub.M,Max] - [D.sub.M,Min]).

The state equation for a charge-controlled memcapacitor in a linear model is described as

dx(t)/dt = [K.sub.1]q(t), (12)

where [K.sub.1] is the mobility factor.

Integrating (12) with respect to time t

x(t) = [K.sub.1] [integral] q(t)dt, (13)

where the initial state is assumed to be zero.

From (9), (11) and (13), the relation between the voltage and charge in a memcapacitor is given by

v(t) = ([D.sub.M,Min] + K [integral] q(t)dt) q(t), (14)

where K = [DELTA]D[K.sub.1] is a constant.

From (3), (4) and (14), the inverse of memcapacitance

[D.sub.M] = [C.sub.M.sup.-l] = [d[phi]/d[sigma]] = [D.sub.M,Min] + K [integral]q(t)dt. (15)


The proposed memcapacitor emulator is designed in the way of composing the input capacitance as a function of applied voltage. Figure 2(a) is the basic idea to implement memcapacitor using buffer and Fig. 2(b) is the equivalent circuit to design the memcapacitor emulator.

The input voltage [] in Fig. 2(a) is given by

[] = [v.sub.A] - [v.sub.B] = [1/Cs] [integral] []dt - [v.sub.B] = [q/Cs] - [v.sub.B]. (16)

where [v.sub.A] is the voltage across the capacitor Cs and [v.sub.B] is the voltage to the input terminal and [] is the input current across the capacitor.

If [v.sub.B] is the proportional to the charge, then

[] = [q/Cs] - mq = ([1/Cs] - m)q, (17)

where [v.sub.B] = mq. Equation (17) implies that the inverse of memcapacitor is [D.sub.M] = [C.sub.M.sup.-1] = ([1/Cs] - m)q. If the value of m is controlled to the time integral of the charge, then, the circuit in Fig. 2 acts as a memcapacitor. To emulate [v.sub.B] in (17), integrator and analog multiplier are implemented, in which the voltage from the buffer and that from the integrator are multiplied using an analog voltage multiplier.

The memcapacitor emulator conducting the operation in Fig. 2 has been designed with commercially available devices as shown Fig. 3. The devices employed for the circuit are OPAMPs (TL082CP), a resistor, capacitors, a diode (D1N4148), and a voltage multiplier (MLT04GP).

In the circuit, the capacitor Cs produces a voltage [v.sub.Cs] with the integration of the current i.

[v.sub.A] = [v.sub.Cs] = [1/Cs] [integral] (t)dt = q(t)/Cs. (18)

Also, the same voltage is obtained at the output terminal of [v.sub.UI].

The current through [R.sub.1] is

[i.sub.R1] = q(t)/[R.sub.1][C.sub.s]. (19)

The output voltage [v.sub.U2] across the integral circuit is

[v.sub.U2] = -[1/[C.sub.1]] [integral] i[R.sub.1] dt = -[[integral]q(t)dt/[R.sub.1][C.sub.1]Cs], (20)

where the negative voltage comes with the diode implemented across [C.sub.1]. The Diode DIN4148 is for keeping the output of the integrator to have negative values. For the proper operation of the proposed memcapacitor, the output of the integrator should be varied only in negative region. However, leakage current in the circuit could have the output of integrator get into positive region undesirably. Whenever the output of integrator gets into positive region, the diode is in forward biased and the output of the integrator becomes zero volts. Thus, the output of the integrator always stays in negative region.

An analog voltage multiplication is performed between the voltages [v.sub.U1] and [v.sub.U2] as

[v.sub.B] = [v.sub.U1] x [v.sub.U2]/2.5 = -Kq(t) [integral] q(t)dt, (21)

where K = 1/2.5[R.sub.1][C.sub.1][Cs.sup.2].

From (18) and (21), the expression of input voltage vin is

[] = [v.sub.AB] = [v.sub.A] - [v.sub.B] = ([1/Cs] + K [integral] q(t)dt q(t). (22)

Observe that equation (22) describes the operation of the memcapacitor in (14) and (17). Thus, the circuit in Fig. 3 is confirmed to be a memcapacitor circuit, in which the inverse of memcapacitance is

Note that the circuit of Fig. 3 is a simple dedicated architecture without a mutator.


The proposed architecture of the memcapacitor emulator has been implemented on a breadboard with off-the-shelf electronic devices, and proper operation has been verified via comparisons with the results of PSPICE simulations. The parameters used for this circuit are [+ or -]5 V power, Cs = 100 [micro]F, [R.sub.1] = 50 K[ohm], and [C.sub.1] = 1 [micro]F.

Figure 4(a) shows experimental results measured on the breadboard circuit at the input terminal [], buffer output [v.sub.U1], and multiplier output voltage [v.sub.B] at 1 V sinusoidal signal with 1 Hz frequency. Figure 4(b) is the oscilloscope display of a pinched hysteresis loop measured from the memcapacacitor emulator.

The PSPICE simulation is performed to measure the voltage across different nodes of the memcapacitor emulator. The input is sinusoidal source with 1 V amplitude and 1 Hz frequency. The waveforms of the input voltage ([]), the buffer output voltage ([v.sub.U1]), integrator output voltage ([v.sub.U2]) and the corresponding multiplier output ([v.sub.B]) are shown in Fig. 5.

Figure 6 shows PSPICE simulations results, when the memcapacitor emulator is driven by sinusoidal source with 1 V and 1 Hz frequency. The flux curve is obtained by integrating the input source which has a similar integrator as U2. Similarly, the charge curve is obtained at node [v.sub.U2]. Since the voltage across [v.sub.U2] is -[integral]q(t)dt/[R.sub.1][C.sub.1]Cs, the actual charge in Coulomb is obtained by multiplying the voltage of [v.sub.U2] by -[R.sub.1][C.sub.1]Cs. The input voltage, flux and charge measured across the proposed memcapacitor emulator are shown in Fig. 6(a) with respect to time axis. The corresponding variation of the flux with respect to charge is shown in Fig. 6(b).

Experiments for the frequency dependency of the pinched hysteresis loops, which is the fingerprints of memcapacitors, have also been performed. Figure 7(a) shows the results when input signals of 1 Hz, 2 Hz, 5 Hz, 10 Hz, and 25 Hz with 1 V sinusoidal signals are applied to the hardware circuit.

Observe that the widths of the pinched hysteresis loops are shrunken as the frequency becomes higher. Figure 7(b) also shows the results of PSPICE simulations, which are similar to the hardware experimental results.


We proposed a new memcapacitor emulator architecture which is useful for circuit applications. The proposed circuit has a dedicated architecture for the memcapacitor emulator, in which mutators are not employed. The circuit has been implemented with off-the-shelf devices, and the operation has been verified to be very close to PSPICE simulation result. Since the proposed architecture has no mutators, the architecture is simple, and can be applied for design applications of complicated memcapacitor circuits.

Manuscript received October 24, 2012; accepted July 9, 2013.

This work was supported in part by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (2012R1A1A2044078), and AFOSR Grant FA 9550-13-1-0136


[1] D. B. Strukov, G. S. Snider, D. R. Stewart, R. S. Williams, "The missing memristor found", Nature, vol. 453, pp. 80-83, 2008. [Online]. Available:

[2] H. Kim, M. P. Sah, C. Yang, T. Roska, L. O. Chua, "Neural synaptic weighting with a pulse-based memristor circuit", IEEE Trans. Circuit and Systems-I, vol. 59, no.1, pp. 148-158, Jan. 2012. [Online]. Available:

[3] H. Kim, M. P. Sah, C. Yang, T. Roska, L. O. Chua, "Memristor bridge synapses", in Proc. of the IEEE, vol. 100, no. 6, pp. 2061-2070, Jun. 2012. [Online]. Available: JPROC.2011.2166749

[4] M. P. Sah, C. Yang, H. Kim, L. O. Chua, "A voltage mode memristor bridge synaptic circuit with memristor emulators", Sensors, vol. 12, no. 3, pp. 3578-3604, Feb. 2012.

[5] Q. Xia, et al, "Memristor-CMOS hybrid integrated circuits for reconfigurable logic", American Chemical Society, Nano Lett. vol. 9, no. 10, pp. 3640-3645, Sep. 2009. [Online]. Available:

[6] J. Borghetti, G. S. Snider, P. J. Kuekes, J. J. Yang, D. R. Stewart, R. S. Williams, "Memristive switches enable stateful logic operations via material implication", Nature Letter, vol. 464, no. 8. pp. 873-876, 2010. [Online]. Available: nature08940

[7] L. O. Chua, "Memristor-the missing circuit element", IEEE Trans. Circuit Theory, vol. 18, no. 5, pp. 507-519, Sep. 1971. [Online]. Available:

[8] M. Di Ventra, Y. V. Pershin, L. O. Chua, "Circuit elements with memory: memristors, memcapacitors and meminductors", Proc. of the IEEE, vol. 97, no. 10, pp. 1717-1724, Oct. 2009. [Online]. Available:

[9] L. O. Chua, "Nonlinear circuit foundations for nanodevices, part I: The four-element torus", Proc.of the IEEE, vol. 91, no. 11, pp. 1830-1859, Nov. 2003. [Online]. Available: JPROC.2003.818319

[10] H. Kim, M. P. Sah, C. Yang, S. Cho, L. O. Chua, "Memristor emulator for memristor circuit applications", IEEE Trans. on Circuit and Systems-I, vol. 59, no. 10, pp. 2422-2431, Oct. 2012. [Online]. Available:

[11] Y. V. Pershin, M. Di Ventra, "Memristive circuits simulate memcapacitors and meminductors", Electron. Lett., vol. 46, no. 7, pp. 517-518, Apr. 2010. [Online]. Available: 10.1049/el.2010.2830

[12] D. Biolek, V. Biolkova, "Mutator for transforming memristor into memcapacitor", Electron. Lett., vol. 46, no. 21, pp. 1428-1429, Oct. 2010. [Online]. Available:

[13] M. P Sah, R. K. Budhathoki, C. Yang, H. Kim, "Expandable circuits of mutator-based memcapacitor emulator", Int. Journal of Bifurcation and Chaos (IJBC), vol. 23, no. 5, pp. 1330017(1)-1330017(17), May 2013.

[14] D. Biolek, Z. Biolek, V. Biolkova, "SPICE modelling of memcapacitor", Electron. Lett., vol. 46, no. 7, pp. 520-522, Apr. 2010. [Online]. Available:

M. P. Sari (1), C. Yang (1), R. K. Budhathoki (1), H. Kim (1), H. J. Yoo (2)

(1) Intelligent Robots Research Center and Division of Electronics and Information Engineering, Chonbuk National University, Jeonju, 561-756, Republic of Korea

(2) Information and Technology Engineering Department, Sangmyung University, Seoul, 1-38 Dongsung-dong, Jongno-gu, Republic of Korea
COPYRIGHT 2013 Kaunas University of Technology, Faculty of Telecommunications and Electronics
No portion of this article can be reproduced without the express written permission from the copyright holder.
Copyright 2013 Gale, Cengage Learning. All rights reserved.

Article Details
Printer friendly Cite/link Email Feedback
Author:Sari, M.P.; Yang, C.; Budhathoki, R.K.; Kim, H.; Yoo, H.J.
Publication:Elektronika ir Elektrotechnika
Article Type:Report
Geographic Code:9SOUT
Date:Aug 1, 2013
Previous Article:The efficiency of algorithms and number of control hierarchy levels of building electronic control system.
Next Article:Efficiency of the electronic license plate recognition systems.

Terms of use | Privacy policy | Copyright © 2022 Farlex, Inc. | Feedback | For webmasters |