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Immunity Characterization of FPGA I/Os for Fault-Tolerant Circuit Designs against EMI.


Due to continuous advances of semiconductor process, the geometrical length of a transistor has been constantly miniaturized. This allows high integration of very complex functional components in a single chip. Such a chip can integrate into a single substrate both analog and digital circuits (i.e., mixed-signal circuits) such as power modules, RF transceivers, microprocessors, digital signal processing units, and so on. This makes the mixed-signal integrated circuits (ICs) produce more electromagnetic interference (EMI) to their ambient environment, which can disturb other circuits sharing the substrate, and other ICs located on the same board or system [1]. Moreover, downscaling the feature size of a transistor requires reducing the supply voltage, which in turn, reduces noise margins of circuits [2]. Therefore, the EMI problem becomes more critical.

Nowadays, electrical and electronic systems are very popular and present anywhere in our life-environment. Noise sources originated from operations of these systems are easily found in cars, airplanes, and houses. Hence, ICs need to be powerful enough to operate without failures in the harsh environment, a property known as the electromagnetic immune ability (i.e., immunity) [3]. The design of ICs to fulfill electromagnetic compatibility requirements is very challenging. For the past few years, many works have been proposed to mitigate electromagnetic emission [4]. On the other hand, a lot of research works on immunity measurement and modeling for ICs have also been published [1-3], [5-14]. Failures in the immunity assessment of circuits during the design phase and before releasing to the market incur penalties such as increased design time and costs, reliability degradation, and shortened lifetime. Eventually, the direct power injection (DPI) method is standardized in IEC 62132-4 [15], which is one of the most commonly used methods for measuring the immunity of ICs in the presence of conducted radio frequency (RF) noise.

The conducted immunity of a widely used 8051-based microcontroller (MCU) was measured by using the DPI method in [8]. In the work, RF noise was injected into the MCU clock pin. If the noise is powerful enough to make a specific MCU output pin change its value, an upset was reported. However, the experiments were only performed at a low-frequency band of external noise (i.e., less than 100 MHz). Su et al. [3] proposed a new method, called Error-Source Switching, to analyze the immunity of an MCU. Accordingly, the RF noise was injected into an I/O pin, and functional modules also worked concurrently. Then, the measurements could show the relationship between the pin under test and the working module being influenced. The immunity measurements of DC current regulators were carried out by using the DPI method in [9]. The RF noise was injected into the output pins of regulators. If the current at the output pin exceeded some tolerance, a failure was confirmed. Wang et al. [10] developed a nonlinear behavior model of a voltage regulator to predict its immunity under continuous RF noises. In their experiments, the RF noise was injected into the power pin of the voltage regulator, and the voltage at its output pin was observed using an oscilloscope to verify its operation. However, there was a mismatch between the simulation and experimental results. It is difficult to model commercial ICs accurately since their internal circuit parameters are not available.

Extended DPI methods were applied to characterize the conducted immunity of ICs at a die or a wafer level [11-14]. Lavarda et al. [11] proposed to characterize the immunity of a simple complementary metal oxide semiconductor (CMOS) amplifier at a wafer level. By eliminating the effects of package parasitic, the measurements help understand the behavior of an IC against continuous disturbances. However, these measurements are not viable for commercial ICs where the devices under test (DUT) at the wafer level are not available. The susceptibility of ICs was also measured by using on-chip noise sensors [12-14]. According to their works, the RF noise was injected into supply rails, and then on-chip sensors captured the real noise values on the supply rails. These approaches are efficient to immunity measurements for power/ground pins. However, there are many input/output pins on a chip, and they are distributed over a chip. Therefore, it is not flexible to apply the on-chip sensor approach to measure the immunity of I/O pins. More importantly, the limitation of this method is the frequency resolution of the noise sensor. As reported in [12], the maximum frequency of noise was about 300 MHz, which is much less than 1 GHz as normal. Moreover, these noise sensors must be fed by separate power supplies, and it must have well-designed noise isolations between the chip under test and sensors. Otherwise, the RF noise will penetrate into sensors.

As aforementioned discussion, we find that previous works performed immunity measurements for ICs by injecting noises into their power lines or input buffers which were running on a fixed supply voltage. Due to benefits in time-to-market, low costs, and more flexibility in hardware upgrade, FPGA-based circuit designs are deployed in a wide variety of application fields such as telecommunications, automotive, medical, and aerospace where the reliability is one of the most important metrics. Thus, the assessment of external noise effects on the operation of I/Os is very important. Practically, FPGA I/Os have the reconfigurable capability to operate with different I/O standards (typically, LVCMOS, LVDS, LVTTL, etc.) and different supply voltages. Thus, the circuit structures of FPGA I/Os are very complicated. Accurate extraction of their parasitic information is a challenging task. In this work, we will characterize the immunity of FPGA I/Os (LVCMOS standard) under different supply voltages, which has not been studied in previous works. Furthermore, the impact of the redundancy-based fault-tolerant circuit (temporal sampling circuit) on the conducted immunity of I/Os is also evaluated and analyzed. Finally, the power consumption of I/O blocks is also measured under different supply voltages. Based on the observed immunity and the power consumption, hardware designers can determine which supply voltage is suitable for I/Os in terms of power budget and reliability requirement.

Our work can be summarized as follows:

* To the best of our knowledge, this is the first work to characterize the conducted immunity of FPGA I/Os under different supply voltages.

* The impact of parasitic components of an I/O pad and an input buffer on the coupling of external noise is theoretically analyzed.

* The effectiveness of the redundancy-based fault-tolerant circuit against the external noise is also evaluated when this circuit is accompanied by I/Os.

* The static and dynamic power consumption of I/O blocks is also measured under different supply voltages. This measurement provides necessary information to constrain both the power budget and reliability of the design.

The paper is organized as follows. Section II analyzes the effect of the coupling path on the external noise coupling to I/Os. Section III describes designs of a circuit under test, an error detector, and a redundancy-based fault-tolerant circuit. The setup model of immunity experiments and the test procedure are covered in Section IV. Experimental results are described in Section V. Finally, we conclude the paper in Section VI.


A. Preliminary of an FPGA I/O

In modern FPGAs, there are many types of I/O buffers that are used to interface with the real world. The circuit structure of an I/O buffer is very complicated. Especially, in FPGAs, I/O buffers can be programmable to operate at different supply voltages and different functions such as input, output, bi-directional, single-ended, and differential-ended buffers. For simplicity, we consider a single-ended I/O buffer in this work. The simple circuit structure and associated parasitic components are illustrated in Fig. 1. [R.sub.p], [L.sub.p], and [C.sub.p] are the parasitic resistance, inductance, and capacitance of the package. [C.sub.g] is the input capacitance of the buffer (gate capacitance). [C.sub.o] is the output capacitance of the buffer. This parasitic information is obtained from the IBIS file that is provided by FPGA vendors.

B. The transfer function of coupling path and I/O buffer In order to understand the behavior of the coupling path and input buffer to the external noise, we investigate the frequency response of these circuits. Fig. 2 illustrates a simple equivalent circuit of the coupling path and input buffer of an FPGA.

[C.sub.g] is the parasitic capacitance of an input buffer. [C.sub.p], [L.sub.p], and [R.sub.p] are the parasitic capacitance, inductance, and resistance of the package associated with that buffer. [C.sub.pcb], [L.sub.pcb], and [R.sub.pcb] are the parasitic capacitance, inductance, and resistance of the printed circuit board (PCB) trace. [R.sub.dpi] and [C.sub.dpi] are resistance and capacitance of the coupling network, which is specified by IEC 62132-4 [15]. The transfer function (gain) of this circuit is a function of frequency. We can express the noise at the input buffer with respect to the noise at the input of the coupling network as (1). H(j[omega]) is the transfer function of the circuit in Fig. 2. [] is sinusoidal disturbance or interference at the terminals of the coupling network, which can be termed as a noise. [V.sub.out] is the noise at the input buffer.

[[V.sub.out] = [] x H (j[omega])] (1)

A frequency-domain representation of the transfer function obtained from SPICE simulation is illustrated in Fig. 3. It is noted that the x-axis in Fig. 3 is plotted on a logarithmic scale. As we can see, a resonant point is observed at 180 MHz where the external noise is strongly coupled to the input buffer. From 180 MHz to 1 GHz, the magnitude of the transfer function is gradually decreased, which means the transfer function attenuates the external noise. The reason behind this behavior is that the parasitic components of the input buffer partly filter out the noise.


In this section, we present the circuit design for the tested system. First, we describe the block diagram of the overall tested system including the circuit under test. Then, the design of a redundancy-based fault-tolerant circuit is covered in the next subsection. Finally, an error detection circuit is described which is used to evaluate the robustness of the tested circuit.

A. Block Diagram of Overall System

The overall design consists of three main blocks, namely, a data generator, a circuit under test (CUT), and an error detection circuit. The block diagram of the overall design is illustrated in Fig. 4.

The data generator is constituted by a single flip-flop (FF) and an inverter on the feedback path, in order to produce a data pattern of altered 0-1-0-1 continuously. The output DO of the data generator feeds the input DI of the CUT by an external interconnection. Although not shown in Fig. 4, there is always an output buffer at DO.

In the real world, the external noise source mostly attacks the circuit via coupling with the input pins of a chip. In order to evaluate the ability of the input buffer against electromagnetic disturbances, we design the CUT that consists of one input buffer and a single FF, named a single FF circuit. At the rising clock edge, the FF of the CUT samples data received from the DI pin. The CUT output is connected to an output pin of the FPGA, which in turn, is connected to an oscilloscope to monitor the output data. Furthermore, the CUT output is also connected to the error detection circuit to verify the correctness of output data. The error detection circuit will be described in Section III-C. For the synchronous circuit, the input data is normally latched into sequential elements before it is processed by the following circuits. That is why we design a simple tested circuit consisting of an input buffer followed by a single FF. In this work, the digital clock manager (DCM) plays a role as a clock divider to provide a 10-MHz clock pulse for all circuits. So, the data sequence generated at the output DO of the data generator has the oscillation frequency of 5 MHz. The external RF noise source can produce glitches on internal signals when it penetrates into the functional circuit. However, not all glitches cause functional failures or errors. In the synchronous circuit, there is a period of time around the rising edge clock (for positive edge triggered FFs) or falling clock edge (for negative edge triggered FFs), called setup and hold times as depicted in Fig. 5, where input data must be stable within the signal margin region. During this period of time, if a powerful glitch attacks the data-path, it can weaken the input data of FF which may lead to functional failure. Out of this window, the glitch does not cause any functional failure because the sequential elements do not sample the input data.

B. Redundancy-based Fault-Tolerant Circuit

The fault-tolerant circuit we implement in this work uses the temporal redundant sampling. This circuit is known as one of the robust single event upset (SEU) and single event transient (SET) mitigation circuits [16-18]. The schematic of this circuit is shown in Fig. 6. The first stage triplicates the sampling circuit, and therefore it can be called the triple modular redundancy (TMR). However, three FFs of this circuit sample input data at three different points of time. That is why it is called temporal sampling. The outputs of three FFs participate in a majority vote to obtain the correct data. In an FPGA, the majority circuit can be implemented by using a 3-input Lookup Table (LUT).

In this work, in order to evaluate the impact of the typical redundancy-based fault-tolerant circuit on the behavior of an FPGA input buffer against electromagnetic disturbance, the single FF circuit in Fig. 4 will be replaced with the redundancy-based fault-tolerant circuit in Fig. 6. Note that the redundancy-based fault-tolerant circuit and temporal redundant sampling circuit can be used interchangeably in this paper.

C. Error Detection Circuit

To determine whether any error occurs at the output of the circuit under test, we design an error detector whose schematic is shown in Fig. 7. This circuit will detect an error by checking the output data of the CUT. Since input data of the CUT is a sequence of 0-1-0-1, output data is considered an error when two consecutive values are identical. By cascading two FFs, two consecutive data samples are captured at the output of the CUT, and they are compared each other by an XOR gate. Normally, the Err_Ind signal is High. If an error occurs, the output signal of the error detection circuit, Err_Ind, goes Low. Fig. 8 shows the timing diagram of the error detector and an error case.


First, we introduce the criteria for the immunity test that includes a testing method, input data pattern for feeding the circuit under test, and how to determine erroneous data. Next, we present the setup model for the immunity measurements. Finally, since I/O pins are assigned for different tasks in the test, the power supply for I/O banks of the FPGA will also be described in this Section.

A. Criteria for Immunity Test

In this paper, the DPI method is used for measuring the immunity of the FPGA input buffer. The transmitted power injected into the FPGA pin is calculated from the forward and reflected powers. The forward and reflected powers are measured at the coupled port and the isolated port of a bidirectional coupler, respectively [19]. The transmitted power is given by (2) [12]:

[[P.sub.trans] = [P.sub.forw] - [P.sub.refl]] (2)

The RF noise is superposed on the input signal of the tested input buffer, which results in a fluctuated signal. When the RF noise power is sufficiently high, the resulting signal level can fall into the unknown region where the logic level might be interpreted incorrectly. This makes the FFs following the input buffer sample incorrect data. The minimum RF power which causes that misinterpretation is used as a measure of the immunity. In this work, the input data is defined as a sequence of 0-1-0-1 with the oscillation frequency of 5 MHz. A misinterpretation is recorded if the circuit following the CUT receives two consecutive samples with the same value (i.e. 0-0 or 1-1).

B. Measurement Setup

In order to inject RF noise into the tested circuit, we use a signal generator (Agilent-8648C [20]) to produce a noise source in a continuous sinusoidal waveform. The output of the signal generator is connected to a high power amplifier (OPHIR-5124 [21]) to provide enough noise power. The maximum RF noise power used in this work is 37 dBm. The power amplifier OPHIR-5124 has an operating frequency range from 20 MHz to 1 GHz, and the maximum output power is 20 W. The power amplifier is connected to a bidirectional coupler (CH-132 [19]). Then, the noise is injected into the CUT through a coupling network (RC circuit). The forward and reflected powers can be measured at the coupled and isolated ports of the coupler CH-132. The test configuration is also described in Fig. 9.

The coupling network consists of a 6.8 nF coupling capacitor and a 100-[OMEGA] resistor. The coupling capacitor is used to protect the power amplifier from the DC component flowing from the CUT. According to the standard IEC 62132-4, the capacitance value of this capacitor can be from 0 to 10 nF. In this work, we choose the 6.8 nF capacitor. Depending on the application, a resistor can be inserted into the coupling network, and it can get the value from 0 to 100-[OMEGA]. In our case, if there is no resistor in the coupling network, the output pin of the FPGA will drive its input pin and a 50-[OMEGA] output impedance of the power amplifier, which causes the current consumption to exceed the maximum driving current of the output buffer. As a result, the voltage swing at the FPGA output pin cannot reach its nominal value. To ensure correct operation, we use the 100-[OMEGA] resistor to limit the driving current of the FPGA output buffer.

C. Power Supplies for the FPGA Chip

In our immunity test, we gradually scale down the supply voltage of an input buffer from the highest nominal voltage of 3.3 V to the lowest nominal voltage of 1.2 V. We need to separate the power supply of the tested I/O buffer from the others. In our setting, we use a programmable DC power supply to feed the I/O bank in which the tested I/O buffer is assigned. Other components and circuits are fed by the voltage regulators that are mounted on the FPGA board. For example, the internal core is powered by 1.2 V. The monitoring output pin connected to the oscilloscope and other output pins connected to the outputs of the error detection circuit are powered by 3.3 V. For the FPGA Spartan-3 (XC3S400-TQ144), two adjacent I/O banks on the same side share the power supply. To implement this configuration, we must assign the tested pin to one I/O bank whereas other pins are assigned to the other I/O bank on the other side. Such a configuration for the immunity test is summarized in Table I.


In this section, first, we present the testing procedure. Second, we describe how to determine the effective gain factor (the loss factor of the coupler and the power amplifier gain) for precise measurements. Then, we present experimental results of the immunity of an I/O buffer that is followed by a single FF. The robustness of the conventional fault-tolerant circuit is also evaluated. Lastly, the power consumption of an I/O buffer is also evaluated for both static power and dynamic power at different supply voltages.

A. Testing Procedure

For the immunity measurement, at each frequency, we increase the RF noise power level until the data pattern at the monitoring pin of the FPGA is different from a given data pattern at its input. The last RF noise power level and RF noise frequency where the CUT operates properly are recorded as the conducted immunity parameters of the CUT. The testing flow chart is depicted in Fig. 10, which follows the standard IEC-621324-4. In our experiments, we set the waiting time ([DELTA]t) to one minute for each test so that the CUT has enough time to response to the function and external RF noise. According to the standard, the initial RF noise power is at least 20 dB less than the maximum level (37 dBm). In our case, we started at 5 dBm. The frequency step is increased by 50 MHz for each testing step.

B. Determine Effective Gain Factor

The frequency response of the power amplifier and the coupler are not constant for a wide frequency band (0-1000 MHz). That means the gain of the power amplifier and the insertion loss of the coupler (from the connector to coupled port) can be varied with the input signal frequency. As a result, the RF power injected into the tested circuit can differ from the calculated value. We combine the amplifier gain and the coupler loss factor into a single factor, so-called the effective gain factor. In order to determine the effective gain factor, we connect the signal generator to the power amplifier, and the amplifier output is connected to the coupler. Then, we inject the RF power from the signal generator and measure the RF power at the coupled port of the coupler with a proper termination at the output port.

Fig. 11 is to provide additional information for us during the measurements. That is a system calibration before starting the measurements. It helps to determine the RF power (generated by the signal generator) injected to the power amplifier, and the forward RF power. Then, the calculated forward RF power is compared with the measured RF power at the coupler port. Therefore, this procedure supports us to adjust the input RF power quickly and ensures that our measurements are correct.

C. Single FF Circuit

Fig. 12 shows the immunity level of the input buffer which is measured in the forward noise power. In this experiment, the input buffer is configured to work at the different supply voltage standards, i.e., LVCMOS12, LVCMOS15, LVCMOS18, LVCMOS25, and LVCMOS33 corresponding to 1.2, 1.5, 1.8, 2.5, and 3.3 V, respectively. We find that the immunity of the input buffer at the supply voltage of 1.2 V is lowest, and it is increased with the increase of the supply voltage. The maximum difference in conducted immunity at the supply voltage of 3.3 V and 1.2 V is 16.8 dB at 600 MHz. The experimental results also show that from 200 MHz to 1 GHz, the conducted immunity of the I/O buffer increases. This is because the high-frequency noises are partly filtered out by parasitic elements of the input buffer, i.e., capacitance, and inductance. As pointed out in Section II, within this frequency range, the magnitude of the transfer function is decreased. In contrast, from 20 MHz to 200 MHz, the trend of the immunity of the I/O buffer decreases, and the immunity is lowest around the frequencies ranging from 150 to 200 MHz. This is because the coupling network mostly transfers the noise power into the FPGA pins, and the resonance points occur at 150 MHz for the immunity curves of 3.3 V and 2.5 V, and at 200 MHz for the immunity curves of 1.8, 1.5 and 1.2V. This is also explained by the model in Fig. 3. Furthermore, there are some fluctuations on one curve of the immunity graph. This highly depends on the effects of the characteristics of FPGA pins as well as the characteristics of the circuit inside.

On the other hand, the immunities of the I/O buffer are also measured in the transmitted noise power, and the graph in Fig. 13 shows the measured immunities. We measure the forward power ([P.sub.forw]) and the reflected power ([P.sub.refl]), then [P.sub.refl] is subtracted from [P.sub.forw] to obtain the transmitted power ([P.sub.trans]). Basically, the transmitted power is less than or equal to the forward power. From Fig. 13, when the I/O supply voltage increases, the immunity of the I/O buffer also increases except for the immunity curves of 2.5 V and 3.3 V from 700 MHz. We find that from 700 MHz to 1 GHz, some points on the immunity curve of 2.5 V are higher than those of 3.3 V. This phenomenon can possibly occur because, at these two supply voltages, the forward noise power reaches the maximum power of 37 dBm. The reflected noise power at 3.3 V is lower than that at 2.5 V, therefore, the transmitted noise power becomes lower.

In short, the immunity of the input buffer at the supply voltage of 1.2V is lowest and increases with the increase of the I/O supply voltage. Moreover, the noise margin of an I/O buffer which is derived from the Spartan-3 specification [22] increases with the increase of the I/O supply voltage as shown in Fig. 14. Note that the RF power dissipation of the coupling network (R and C) is not reported. As the standard recommendation, the values of the resistor (100 [OMEGA]) and the capacitor (6.8 nF) used for the measurements are stated.

D. Redundancy-based Fault-Tolerant Circuit

In this part, we measure the conducted immunity of the FPGA input buffer when the redundancy-based fault-tolerant circuit is used as a data sampling circuit. That means we replace the single FF circuit in Fig. 4 with the redundancy-based fault-tolerant circuit, and then measure the immunity of the input buffer. Fig. 15 shows the immunity of the input buffer (at 3.3 V) corresponding to the two data sampling circuits: (1) the single flip-flop, (2) the fault-tolerant circuit using the temporal sampling technique. We find that the immunity of the redundancy-based faulttolerant circuit is better than the single FF by approximately 4 dB when the external noise frequency is less than 400 MHz as shown in region I. When the noise frequency is higher than 400 MHz, the immunity of the fault-tolerant circuit is not better than the single FF circuit. As illustrated in the region II of Fig. 15, the immunity of the temporal sampling circuit is lower than that of the single FF circuit by 1.5 dB at 550 MHz. The possible reason behind this is that when the noise frequency is increased, the probability of any two of the three FFs in the temporal sampling circuit capturing incorrect data becomes higher. Therefore, the probability of having erroneous output at the majority voter is higher.

Fig. 16 demonstrates a failure when the tested I/O is powered by 3.3 V. The input signal is a rectangular signal with an amplitude of 3.3 V. The continuous sinusoidal noise has an amplitude of 1.4 V. When the input signal is at logic-1, the negative amplitude of the noise signal is considered. In Fig. 16, at the points (1), (2) and (3), the amplitude of the noise signal reaches -1.4 V, so the superposed signal amplitude is 1.9 V which is lower than the minimum allowable input voltage of logic-1 for LVCMOS33 (i.e., 2.0 V). That means if FFs capture data at these points, the metastable phenomenon might occur in these FFs. If any two of three FFs capture incorrect data, the voter produces unexpected data at its output. A similar explanation can be applied to the input signal with logic-0. In this case, the positive amplitude of the noise signal is considered, and the voltage level of 0.8 V is utilized as the maximum allowable input voltage of logic-0 for LVCMOS33.

On the other hand, the immunity of the input buffer at the supply voltages of 2.5 and 3.3 V are also evaluated and compared as shown in Fig. 17. Similar to the result in Section V-C, the immunity of the input buffer at the lower voltage is also lower than that at the higher supply voltage.

In summary, the immunity trend of the fault-tolerant circuit is similar to that of the single FF circuit. Moreover, at the low-frequency band below 400 MHz, the immunity of the input buffer with the fault-tolerant circuit is improved when compared with that of the input buffer followed by the single flip-flop. Nevertheless, at a higher frequency band, the temporal redundant sampling circuit does not improve the immunity of the input buffer. Finally, the single FF and the TMR circuit should be placed as close to the I/O block as possible, so the difference in the routings between different configurations is not significant. Moreover, the general purpose I/O blocks have the same circuit structure, and they also have the same parasitic attribute. Therefore, our experimental results can be applied to other I/O blocks.

E. The power consumption of IO Block

This section discusses the power consumption of I/O blocks (IOBs) which operate at different clock frequencies and different supply voltages. The characterization of the power consumption for IOBs is useful to designers when they want to take both the I/O immunity and its power consumption into consideration to verify their design targets.

The measured static power dissipation of one IOB of the FPGA Spartan-3 is shown in Fig. 18. The static power dissipation is strongly dependent on the I/O supply voltage. The static power dissipation slowly increases when increasing the supply voltage from 1.2 V to 1.5 V, and from 1.5 V to 1.8 V. However, the increase of power consumption becomes more rapid when the supply voltage is changed from 1.8 V to 2.5 V, and from 2.5 V to 3.3 V. The increment is approximately 19.5 times from 1.32 [micro]W at 2.5 V to 25.71 [micro]W at 3.3 V.

The static power dissipation always exists in the circuit as long as the circuit is powered on. In contrast, the dynamic power dissipation only exhibits when switching activities occur inside the circuit. The dynamic power dissipation is a function of the supply voltage, switching frequency, and load capacitance. This dependency is clearly depicted by the measurement results in Fig. 19. Note that the dependency of load capacitance is not taken into account in this paper. When downscaling the supply voltage of IOBs, their dynamic power consumption is significantly decreased. Particularly, at the operating frequency of 60 MHz and the supply voltage of 1.2V, the dynamic power dissipation of the IOB is 1.28 mW, which is approximately 7.8 times less than the one at 3.3 V, i.e., 10 mW. The reduction in dynamic power dissipation can be 11.6 times if the IOB is configured to operate at 5 MHz and the supply voltage of 1.2 V instead of 3.3 V. It is noted that we only measured the power dissipation at the operating frequencies below 100 MHz, which is targeted by the low-cost Spartan-3 FPGA families.

In short, based on all the above discussions, the immunity of I/O buffer considerably decreases when reducing the I/O supply voltage. However, a benefit that can be obtained by downscaling the supply voltage is the reduction in power dissipation of IOBs.


This paper has characterized the immunity of the I/O buffer of the FPGA Spartan-3 with different supply voltages under two scenarios: (1) an I/O buffer followed by a single FF, and (2) an I/O buffer followed by a conventional redundancy-based fault-tolerant circuit. The experimental results showed that when scaling down the I/O supply voltage from 3.3V to 1.2V, the immunity of the I/O buffer drastically decreases about 16.8 dB. Importantly, this paper showed that a commercial FPGA chip with a widely employed redundancy-based fault-tolerant circuit can improve its immunity under the conducted noise in the frequency band less than 400 MHz.

We also presented the transfer function of the coupling path and input circuit of an I/O buffer, which was used to explain variations in the conducted immunity of an FPGA I/O buffer. Finally, although the immunity of the I/O buffer decreases when reducing the I/O supply voltage, 11.8 times reduction is observed in dynamic power dissipation, and it can be an attractive design choice in power limited applications.


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Van Toan NGUYEN (1), Minh Tung DAM (1), Jungmin SO (2), Jeong-Gun LEE (1)

(1) Department of Computer Engineering, Hallym University, South Korea

(2) Department of Computer Engineering, Sogang University, South Korea

Digital Object Identifier 10.4316/AECE.2019.02005

I/O Standard              Power Supply              I/O    Function

LVCMOSX                   DC Programmable Supply           I/O under
(X: 12 [right arrow] 33)  (Variable: 1.2 to 3.3 V)         test
LVCMOS33                  3.3 V                     2, 3   function
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Author:Nguyen, Van Toan; Dam, Minh Tung; So, Jungmin; Lee, Jeong-Gun
Publication:Advances in Electrical and Computer Engineering
Date:May 1, 2019
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