HDL ENHANCES FUNCTIONAL VERIFICATION SOFTWARE TO IMPROVE SOC DESIGN PRODUCTIVITY.
@HDL, Inc. has introduced @Verifier version 2.5, an enhanced version of the company's functional verification software. @Verifier finds the toughest design problems by an innovative application of automatic formal model checking and automatic functional vector generation. The @Verifier version 2.5 has been enhanced to improve overall performance and capacity when running large System-on-Chip (SoC) designs.
"Our team develops advanced communication SoC designs. We use extensive simulation as the basis for the functional verification of these systems," stated Dr. Vallath Nandakumar, design engineering section manager at AMD (NYSE:AMD) in Sunnyvale, California.
"@Verifier used automatic property extraction and detected several state machine control logic design bugs which were not immediately uncovered during our simulation-based diagnostic testing."
"Today's design complexity requires not only faster simulation, but also demands intelligent verification strategies to improve productivity," stated Badru Agarwala, @HDL co-founder, President and CEO. "The AMD results validate that @Verifier can augment the existing verification flow and automatically detect complex bugs not uncovered during simulation."
Specific improvements in @Verifier 2.5 include hierarchical model checking, support for both bounded and un-bounded algorithms, and an advanced algorithm to greatly speed up property checking. These improvements result in delivering over four times capacity increase and faster run times.
Verifier automatically extracts properties from Verilog RTL designs to uncover such problems as multiple clock domain synchronization errors, Finite State Machine (FSM) deadlock, and Code Reachability errors. In addition to detecting these tough problems, the automatic property extraction can find an extensive set of other bugs, including one-hot drivers and decoders, parallel and full case statements, unreachable and terminal state, never reachable conditions and codes, FIFO read/write and reset errors, index-out-of range, and stuck at zero/one.
"This release of @Verifier also includes improvements to increase verification productivity by automatically identifying many other synchronization schemes during clock domain analysis. Additionally, failing properties from @Verifier can be debugged more rapidly due to the tight coupling with logic cone tracing now available in our @Designer product," stated Tarak Parikh, @HDL Vice President of Product Engineering.
Verifier 2.5 is available immediately for use with engineering workstations running Solaris and Linux operating systems. The software is available for download and evaluation from the company website. In conjunction with the @Verifier version 2.5 release, @Verifier-PLUS is now also available. @Verifier-PLUS includes one network license of @Verifier and three network licenses of @Designer. @Verifier and @Verifier-PLUS are available as a time-based subscription license or as a perpetual license, starting at $30,000.
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|Title Annotation:||@Verifier 2.5|
|Comment:||HDL ENHANCES FUNCTIONAL VERIFICATION SOFTWARE TO IMPROVE SOC DESIGN PRODUCTIVITY.(@Verifier 2.5)|
|Publication:||EDP Weekly's IT Monitor|
|Article Type:||Product Announcement|
|Date:||Feb 4, 2002|
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