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Going Beyond Copper Interconnects.

The use of copper interconnect technology in integrated circuits uncovers a host of new challenges.

It has been nearly a year since IBM announced it developed a commercially viable process for using copper to interconnect integrated circuit elements. And while the process may have seemed novel a short time ago, copper interconnects has since become a standard feature of the current crop of new IC designs.

It's time to look ahead to see what semiconductor researchers are cooking up for the next generation. What new materials are about to become available? Why do we need them? How will we process them?

"We needed copper in the first place to decrease the interconnect resistance," says Shyam Murarka, core director at the Center for Advanced Interconnect Science and Technology at Rensselaer Polytechnic Institute, Troy, N.Y. Murarka's group at RPI was created a few years ago with funds from the newly formed Sematech. They were funded as a SCOE (Sematech Center of Excellence) with interconnect-related research, such as copper interconnect, low-K dielectric, and chemical mechanical planarization (CMP), as their specific mission.

Interconnects exhibit resistance-capacitance coupling, which causes delay in the circuit. If you can reduce the capacitance, as well as the resistance, you can achieve an even greater speed gain. A material's dielectric constant (K) determines the parasitic capacitance it introduces when used to insulate a transmission line, which is really all an interconnect via is. "We need copper to decrease the resistance and we need low-K dielectrics to decrease the capacitance," says Murarka.

"First we tried polymers, but IC fabricators have settled on a commercial material called SILK [a product of Dow Chemical, Coming, N.Y.], which brings the dielectric constant down from 4 for silicon dioxide to about 2.7. People are looking for dielectric constants of 1.5 in 5 to 7 years, so another generation of these materials will have to be developed."

SILK stands for "Silicon Low-K." SILK's dielectric constant of 2.7 brings the distributed capacitance between these interconnect vias and adjacent structures down by almost 33%.

Another promising low-K material is aerogel made of silicon dioxide. While aerogels are made of relatively high-K silicon dioxide, they consist mainly of a lot of trapped air bubbles. Air's dielectric constant is very close to unity, which is theoretically as low as you can go. If you can mix silicon dioxide with lots of air bubbles, then you can get a very low dielectric constant.

Murarka's group is also looking at polymers and how to get them to have a dielectric constant less than 2. So far, the most promising low-K polymer is Teflon, with a dielectric constant of 1.9. However, Teflon is not the best choice from a materials-processing point of view.

The most important property a candidate material can have is, of course, that it's a good insulator. It also has to be compatible with the other materials the IC will be made of, it should be processable with the metal on it, and it should be reliable when built into a complex thin-film structure along with other materials.

Although planarization is important for making reliable semiconductor structures that perform as needed, Murarka believes it will be even more critical in the future.

"There are two ways to look at CMP," he says. "If you look at what industry has been doing, they have made CMP a bread-and-butter tool for fabricating multilevel structures. It makes those multilevel structures possible.

"We also have to look at where we can take this technology in the future," says Murarka. "That requires a great deal of fundamental knowledge, which is currently missing." For instance, suppose in 2010 you have a device that is 0.5- or 0.6-[micro]m wide. You will want the oxides and metals polished at a level where you require 10- to 15-[Angstrom] planarity. Silicon wafers will require planarity on the level of 1 atomic dia. When you have those requirements for planar devices, especially in the first 2 to 3 levels, then you can understand how to control CMP much better.

"We have to understand how to optimize the process for each given set of materials. That is the fundamental knowledge we will need if we want to keep using CMP for the future."

In the past, semiconductor fabricators have used CMP to smooth inorganic materials, such as silicon dioxide and copper. These are hard materials compared to polymers. If they are going to use polymers, which are relatively soft, or aerogels, which are porous, for low-K dielectrics then they have to learn about polishing these materials in conjunction with copper.

For copper to fully achieve its promise as a low-resistivity interconnect material, all of the via surfaces have to be tailored to minimize scattering of the electrons--even the vertical side walls. If the metal surfaces are not tailored properly, inelastic scattering of electrons at the surface will become very high and the resistance will go up.

By 2007 or 2010, copper interconnect at the first two levels will have a thickness near the mean free path of the electrons in the copper. That means the surfaces will dominate the resistance of the material. Predictions show that if semiconductor engineers can achieve 75% elastic scattering, then they can take copper all the way to 200-to 300-[Angstrom] thickness without increasing the resistivity.

Murarka's research involves improving the effectiveness of copper interconnect. The copper interconnect process starts with planarizing the dielectric. The next step is to cut holes through the dielectric in which to deposit copper to make electrical contact with the lower, active levels, and trenches to fill with copper for interconnect vias.

The interconnect metal must have two properties: it has to adhere to the dielectric and cannot diffuse into the dielectric. However, copper doesn't adhere well and it does diffuse. The solution to this problem has been to sandwich another material between the copper and insulator that acts as a diffusion barrier and adhesion promotor.

Semiconductor fabricators currently use tantalum or tantalum nitride for this job. Unfortunately, these materials have high electrical resistance ranging from 150 to 300 [micro]ohm-cm, and only work when they are at least 100-[Angstrom] thick. Because there is 100 [Angstrom] of high-resistivity material taking up space in the interconnect trenches, the copper layer has to be thinner, which raises its resistance and partially defeats the purpose of having copper in the first place.

Murarka is looking for a diffusion barrier/adhesion promoter that is no more than a few monolayers thick, or no more than 20 to 30 [Angstrom]. The answer may be to deposit a material along with the copper that, when it contacts the insulating layer surface, reacts with it to give adhesion, as well as barrier properties. To deliver this material, it would be dissolved in or alloyed with the copper, and it must not increase the copper's resistance.

"We started this research about 10 years ago with funds from IBM," says Murarka. "At this point, we have shown that you can add material into the copper in such a way that it can diffuse to the surface of the insulator. It then bonds with the insulator and provides the barrier properties."

You find there are only a few choices for this material when you consider the physics and thermodynamics of the situation. The best candidate seems to be magnesium added at 2 atomic % of magnesium to copper. The other choice is 1 to 2% aluminum. Adding 2% magnesium to the copper results in a via with a resistivity of less than 2 [micro]ohm-cm, which is 100 times better than is achievable using tantalum nitride as a barrier/promoter. Using aluminum is about 50 times better than tantalum nitride.

"Research is one thing," says Murarka. "The real question now is whether we can make it happen on production devices."

Is there an alternative to silicon that is ideal for today's popular semiconductor applications? Mike Mazzola, associate professor of electrical and computer engineering at Mississippi State Univ., Starkville, Miss., is working on one. Specifically, he's using silicon carbide in smart-power and high-frequency applications at the Mississippi Center for Advanced Semiconductor Prototyping.

"Our capabilities range from state-of-the-art silicon carbide epitaxial thin-film growth, full photolithography, reactive ion etching, and metallization--all of the processes that you use to fabricate devices in silicon carbide."

Unlike the familiar narrow bandgap semiconductors, such as silicon, gallium arsenide, and germanium, silicon carbide is a wide bandgap semiconductor. The bandgap of one of the most important forms of silicon carbide, known as 4h, is about 3.2 eV. This is about 3 times larger than that of silicon. Other interesting properties of silicon carbide are:

* It's extremely hard.

* It's chemically very inert.

* It does not melt at atmospheric pressure, but sublimates at temperatures more than 2000 [degrees] C.

* Dopants do not migrate because the diffusion coefficients are far too small.

* It has high electric-field breakdown strength and thermal conductivity.

* Researchers have demonstrated a full doping range for the material, from semi-insulating (resistivity [is greater than][10.sup.12] ohm-cm) to full N- and P-type doping.

* There are single-crystal silicon carbide substrates commercially available.

All in all, silicon carbide is ideal for tough applications in high-temperature electronics, radiation hard electronics, highpower densities, and at high frequencies. Underground applications, for example, are areas where wide bandgap semiconductors have been developed for some time.

Because there is no practical diffusion, epitaxy becomes a critical technology for silicon carbide devices. All of the active layers tend to be grown epitaxially, much the way it is done for III-V semiconductors.

The material's chemical inertness cannot be over emphasized. Wet etching is not a practical processing step. Reactive ion etching (RIE) is the only practical way to etch features into it, but the approach is a practical one. Commercial RIE systems developed for silicon can easily be configured for silicon carbide. In fact, MCASP has a Lamm 9400 coming on line fight now. It will be a better RIE system used for processing silicon carbide.

Silicon carbide material quality is still far from the quality of readily available silicon wafers. Single-crystal silicon carbide substrates are commercially available from multiple vendors, but these substrates have bulk defects that can and do propagate into the epitaxial layers. This fact limits the size of the devices that can be fabricated in with acceptable yield. Current technology, however, is quite adequate for small-scale integrated circuits. General Electric, Fairfield, Conn., for example, has introduced an operational amplifier made with 100 transistors, which they can produce with acceptable yield.

"People are running into problems at millimeter-size devices," Mazzola reports. "One of the big things we have to take advantage of is smallscale integrated circuits, such as smart-power ICs, which I think will be a very fruitful area for silicon carbide. We have to make sure that we operate in the parameter ranges where silicon carbide exceeds what silicon can do."

Silicon carbide's high native resistivity can also be exploited readily. There are many applications for having an insulating or semi-insulating material that is homoepitaxial all the way. This situation is already exploited in gallium arsenide and other III-V semiconductors where semi-insulating substrates are readily available.

For example, having a high-resistivity, semi-insulating substrate reduces the parasitic capacitance in RF and microwave devices to tolerable levels. It can be a deciding factor in making practical high-[F.sub.T] RF devices.

"There is no question that we will be growing good SC crystals in less than 10 yr," says Mazzola.

Silicon carbide suppliers have made tremendous advances in recent years. It is widely viewed that the reason silicon carbide wafers are at 50 mm now and heading for 7.62- to 10.16-cm substrates in the next 3 yr--in contrast with the silicon industry's current transitioning to 300-mm sizes--is because silicon carbide technology is less mature. In many ways, it is where silicon technology was 30 to 40 yr ago.

Fundamentally, the reason there is still so much work to be done on silicon carbide technology is that the processes involved are inherently more difficult. The growth of bulk crystals always occurs above 2000 [degrees] C. That is always going to be a more challenging process to control.

Silicon carbide epitaxial growth is done at 1600 [degrees] C or hotter, at least for the hexagonal group. It is possible to work with the 3c form at a somewhat lower temperature, but the temperature processing is high compared to what is done with silicon.

Solving the high-processing temperatures and limitations on useable processes takes time. The issues, however, are with process development rather than with fundamental solid-state physics.

With the immaturity of silicon carbide process technology, it is surprising to see the wide range of device types that have already been built using this material. While Mazzola works on processing problems, his colleague Jeff Cassady works at MCASP on device-fabrication issues. He reports a huge laundry list of device types that have been demonstrated, including: Schottky barrier diodes, high-voltage PN junction diodes, Power BJT (bipolar junction transistor), GTOs (gate-turnoff diodes), MESFETs, static induction transistors, RF power devices, operational amplifiers, UV photodiodes, lateral power MOSFETs, and JFETs. In fact, you can do just about anything in silicon carbide that you can do in silicon.

"I think that right now we have a bias for non-MOSFET-based technology, like BJTs and JFETs," says Mazzola. "These devices avoid the problems people have with channel mobilities and oxide interfaces. Currently, there is more promise with bipolar technology for power. And it's not that MOSFETs aren't feasible, there just seem to be some trickier issues to solve."

Gallium nitride is another wide bandgap semiconductor that is also receiving attention. There is a substantial community that believes this material is an important wide bandgap semiconductor and that silicon nitride will have diminishing importance. Gallium nitride is already having a great commercial impact on optoelectronics, and will continue to do so.

Mazzola expects that silicon nitride's main impact on optoelectronics will mostly be as a substrate for gallium nitride LEDs. One problem gallium nitride has is that there is no economical, high-quality, free-standing substrate. The only choices are to do heteroepitaxy of gallium nitride onto either sapphire or silicon carbide wafers. Of those two, Mazzola says silicon carbide is superior because it has a smaller lattice constant mismatch to gallium nitride and can be doped to become highly conductive. Having a highly conductive substrate leads to the possibility of making vertical LEDs, which are more cost-effective to produce. In fact, much of the improvement in silicon carbide wafers has been driven by the need for high-quality substrates for heteroepitaxy of gallium nitride LEDs.

Will copper remain for the future? "My belief is that copper will take us all the way to 0.03 gm," says Murarka, "provided we can passivate the surfaces to keep the resistance low."

Above 1 GHz frequencies--which many high-performance ICs already approach--screening effects begin to become important. High-frequency electromagnetic waves can penetrate only so far into any conductor. Skin depths for copper at 1, 10, and 100 GHz are approximately 3, 0.7, and 0.15 [micro]m, respectively. Material farther in simply does not participate in conduction.

IC designers will have to tailor their interconnects to take this screening effect into account. "We will have to worry about those effects about 5 to 6 years from now," Murarka predicts. "Some engineers are already working on devices made of gallium arsenide and indium phosphide that work into the 40-GHz range. They say that they can tailor copper easily for their purposes."

If we can solve these problems, then we will have answers all the way through the life of the silicon technology. The challenge then becomes whether we can find alternatives to copper.

There are many things we can try in the future, such as designing the interconnect so it works more efficiently than the way we are doing it now. Today, we lay down the circuits and then the interconnect on top. Can we optimize the interconnect before we lay out the circuits? If so, how can we do it and how can we build the resulting circuit designs?

Another idea is to forget electronic transmission. However, the biggest mystery is not whether we can do wireless or photonics, but whether we can do it with silicon devices that are small enough. Today, optoelectronic devices have to be relatively huge to operate.

There is also talk of building interconnects in 3D, as well as 3-D active devices. These technologies, however, will require more engineering development than science development.

There are many questions about 3-D ICs, the biggest being how we will dissipate the heat generated by these 3-D circuits. One possible answer may be silicon carbide.

"My prognostication," says Mazzola, "is that in the next 5 yr there will be a rapidly growing commercial business for purely silicon carbide power devices. In 5 yr or more, there will be silicon carbide RF and microwave devices, used mostly for defense applications, operating in the L and X bands. You probably will not see gallium nitride devices in those applications. There will, however, be multiple vendors for silicon carbide power devices for a wide range of niche applications."
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Author:Masi, C.G.
Publication:R & D
Geographic Code:1USA
Date:Jul 1, 2000
Words:2869
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