GaAs radiation hardness.
The nuclear radiation encountered in certain military and space environments and the nuclear industrial field is the most demanding ambient to which semiconductor devices are exposed. The four major nuclear and space radiation threat categories are total dose and dose-rate effects of ionizing radiation, neutron degradation effects and single-event upset (SEU) due to protons and heavy ions.
TOTAL IONIZING DOSE EFFECTS
Total ionizing dose effects are particularly acute in semiconductor FET technologies that employ metal gates on layers of insulating material (e.g., MOSFETs and MISFETs). In these devices, the charging of native or deposited insulators may result in pinching off (i.e., reduction) of channel current and increases in parasitic current leakage at the semi-conductor-insulator interfaces.
GaAs devices are highly immune to total ionizing dose effects for two reasons. First, typical device technologies do not employ gate oxides or insulators. Second, and more fundamentally, the surface Fermi level is pinned by the surface. For ionizing radiation, the pinned surface of GaAs provides the ultimate hardness, rather than the MESFET device structure. GaAs MES, FETS, JEFTs and bipolar devices survive well past 100 MRads of ionizing radiation with only minor changes in device parameters.
Heavily doped GaAs FETs with pn-junction or Schottky-barrier gate structures are not susceptible to the effects of prolonged exposure to ionizing radiation. Because discrete GaAs FETs are not susceptible to total doses of ionizing radiation up to [10.sup.8] Rad(GaAs), the same performance is expected for GaAs planar integrated circuits; indeed, ICS of ring oscillators, flip-flops, buffers, frequency dividers and static RAMs from SSI to LSI complexity have operated without serious degradation of electrical performance up to total doses of [10.sup.8] Rad(GaAs). GaAs MESFETs and MMIC amplifiers have also demonstrated functionality up to [10.sup.8] Rad(GaAs), but with noticeable degradation of noise figure and RF gain above [10.sup.7] Rad(GaAs).
IONIZING DOSE-RATE EFFECTS
An ionizing dose rate generates electron-hole pairs in GaAs. Thus, the semi-insulating substrate material in which the FETs are fabricated for integrated circuit design becomes conductive during ionizing radiative exposure. A photocurrent, called the "substrate shunting current," is generated between source and drain contacts. This current was shown to exceed the primary photocurrent of the pn-junction or Schottky-barrier gate junction on the secondary photocurrent of the FET. The first-order logic upset current is therefore considered to be the substrate shunting current [l.sub.ps] rather than small primary photocurrent [l.sub.pp].
EFFECTS BY NEUTRONS
Ion implantation of n-type impurities into semi-insulating GaAs is used to fabricate depletion-mode and enhancement-mode GaAs JFETs and MESFETs. The ion-implantation process results in an impurity distribution that varies spatially within the FET channel region. As a general conclusion of these results, FETs with a uniform and high doping concentration offer the best tolerance to neutron irradiation. Such devices can be realized with MBE growth.
GaAs LSI devices and eventually LSI logic circuits, based on either JFET or MESFET technology, should be capable of operating up to about [10.sup.15 N/cm.sup.2] without suffering failure or significant performance degradation. The failure threshold of optimized devices with channel doping increased to [10.sup.18cm.sup.-3] is projected to extend into the [10.sup.15] to [10.sup.16 N/cm.sup.2] range. Linear MMICs can be expected to be somewhat less tolerant than digital ICs and measurements have indicated noise and gain degradation of GaAs MESFET microwave amplifiers beginning at [10.sup.14 N/cm.sup.2].
GaAs charge-coupled devices (CCDs) probably have an even lower failure threshold and suffer unacceptably large increases in transfer inefficiency between [10.sup.12] and [10.sup.13] [N/cm.sub.2] as a result of the shallow introduced trapping levels.
PHENOMENA IN GaAs JFET ICs
The first experimental results of prototype GaAs ICs with respect to SEU performance reported the upset cross section of resistive-load, 256-bit, static RAMs to 40-MeV protons. A comparison of this result with Si technology placed the hardness of the GaAs in the range of Si NMOS circuits, above that of bipolar Si memory circuits. The concept of resistive decoupling of memory cells was successfully applied to a Si CMOS static RAM to provide immunity to single-event upset. In a recent development, complementary GaAs integrated circuitry was explored with intracell decoupling resistors and demonstrated an SEU immunity to 40 MeV protons.
To determine the errors per bit-day performance of ICs when exposed to heavy ions, measurements of the upset cross section are required in addition to the linear energy transfer (LET). By using an approximation for cosmic ray upset rates outside the earth's geomagnetic cut-off, the best value for a GaAs 256-bit complementary SRAM is then R = 2.9 x [10.sup.6] upsets/bit-day. If we could increase the effective value of [Q.sub.c] by circuit innovations, invulnerability to SEU would become a realistic possibility.
The outstanding total dose ionizing radiation hardness of GaAs integrated circuits, in contrast to Si MOS devices, is attributed to the pnjunction or Schottky-gate structure, which is free of charge buildup, the detrimental failure mechanism in the dielectric MOS gate structure. Figure 1 presents a comparison of performance for various Si ICs with that of digital and linear GaAs ICs. A value of [10.sup.8] Rad(GaAs) is a safe level for GaAs ICs, which exceeds that of Si ICs by a factor of 10 to 100. So far, the logic upset dose rate to pulsed ionizing radiation of 20 ns or less was demonstrated to fall into the range of [10.sup.10] to [10.sup.11] Rad(GaAs)/s as predicted for devices of 1-mum channel length and taking into account the substrate shunting currents.
GaAs JFETs in direct coupled FET logic design with low supply voltage (less than 2 V) display a prompt response and are free of long-term radiation transients. The distinct behavior of this technology is ascribed to the forward-biased operation of the gate and the low supply voltage, thus avoiding back-and side-gating. In comparison, only Si CMOS-SOS technology can complete in this range, as shown in Figure 2.
In the neutron radiation environment, most GaAs and Si ICs can tolerate about [10.sup.15 N/cm.sup.2] before displacement damage alters the mobility, carrier concentration and lifetime of minority carriers in vital portions of transistor operation. Figure 3 lists the displacement damage thresholds for GaAs and Si IC technologies. Improvement beyond [10.sup.15] [N/cm.sup.2] fluences can be achieved in some of the transistor designs by increasing the doping concentrations, thus reducing the effects of carrier removal.
When scaling device size, thus decreasing the critical charge for SEU, the vulnerability of Si and GaAs VLSI technology to SEU from heavy ions of cosmic rays and protons imposes limitations to space applications. The SEU mechanism in GaAs logic designs requires additional study to clarify the charge collection in devices fabricated on semi-insulting substrates. By using an approach analogous to that of Si CMOS SRAMs, complementary GaAs JFET SRAM design has achieved SEU rates of [10.sup.-6] errors/bit-day for heavy ions.
The complementary GaAs E-JFET memory cell offers the prospect of SEU immunity with further research of device scaling and resistive decoupling in memory cells. System needs will drive this development because they demand the combined and balanced properties of extremely high-speed operation and superior radiation-hardness capability.
PHOTO : FIGURE 1 REPORTED (SOLID) AND PROJECTED (DOTTED) TOTAL DOSE FAILURE THRESHOLD OF GaAs AND Si ICs
PHOTO : FIGURE 2 REPORTED (SOLID) AND PROJECTED (DOTTED) DOSE-RATE LOGIC UPSET THRESHOLD OF GaAs AND Si ICs
PHOTO : FIGURE 3 REPORTED (SOLID) AND PROJECTED (DOTTED) NEUTRON DISPLACEMENT DAMAGE THRESHOLD OF GaAs AND Si ICs
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|Title Annotation:||EW Design Engineers' Handbook & Manufacturers Directory; gallium arsenide semiconductors|
|Publication:||Journal of Electronic Defense|
|Date:||Jan 1, 1992|
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