GL Announces Asynchronous Transfer Mode (ATM) BER Testing for T1 E1.
He added, "GL has various tools for the analysis and test of ATM. For example: ATM Analyzer, Inverse Multiplexing over ATM (IMA) Analyzer, T3 E3 ATM Analyzer, OC3 STM1 OC12 STM4 ATM Analyzer and many others. A recently added application is ATM BERT for T1 E1. A typical ATM BERT application is the verification of end to end integrity in an ATM virtual connection as shown below:
Mr. Vadalia explained, "In the above figure, there is an implicit end to end connection between the endpoints. ATM is inherently connection oriented, therefore any traffic that relies on connections is easily accommodated (adapted), i.e. voice, modem, and fax. Traffic that is inherently connectionless must be adapted, thus the necessity of higher ATM Adaptation Layers, or AAL. To test an end to end ATM derived virtual circuit, one can use GL's ATM T1 E1 BERT software with any of GL's T1 E1 platforms".
He continued, "The ATM BERT application transmits a BERT pattern using the simplest ATM Adaptation Layer, i.e. AAL0. The BERT pattern is inserted in its entirety into the 48 byte payload of the cell. It allows an ATM virtual circuit to be tested by sourcing test traffic and verifying at the receive end. Other features are: Bit Error Insertion, Looping back incoming traffic (using T1 E1 Loopback), and configuring ATM headers for UNI & NNI interfaces. The application is capable of generating various Pseudo Random Bit Sequence (PRBS) patterns, all ones, all zeroes, alternate ones & zeroes, 1:1, 1:7, and user-defined bit patterns. In addition, single bit error insertion, auto error insert rate from 10-2 to 10-9, invert & non-invert selections, and scrambling options (according to ITU-T G.804) are provided".
* User-defined header configuration supported
* User-defined traffic rate to the accuracy of 1% of total bandwidth
* Supports different PRBS patterns, All one's, All zero's, alternate 1's and 0's, 1:1, 1:7, and User -defined pattern. User defined pattern length can be 2 to 32 bits in length
* Supports inverting payload data, and scrambling. Scrambling is according to ITU-T G.804
* Supports single bit error insertion, and error rate insertion.
* Provides detailed statistics such as Rx/Tx cell count, total cell count, rejected cell count, pass cell count, idle cell count, cell rate, and HEC error count
* Provides throughput details, error, and alarm LEDs for easy analysis
* Tx and Rx settings for multiple ports can be independently controlled or coupled
* Capable to save and load the configuration settings
Brief Description of T1 E1 ATM BERT Features: ATM Header Configuration
The GUI provides configuration of ATM header fields such as GFC (Generic Flow Control), VPI (Virtual Path Identifier), VCI (Virtual Channel Identifier), PT (Payload Type), and CLP (Cell Loss Priority). ATM header fields for UNI will have GFC (Generic Flow Control) enabled, while for NNI interface GFC field is disabled.
Selecting BERT Patterns (Payload)
Payload at the Tx configuration allows user to select specific Bit Error Rate test pattern for transmission. T1E1 ATM BERT support various BERT patterns; QRSS, 29-1, 211-1, 215-1, 220-1, 223-1, all ones, all zeros, 1:1, 1:7, alternate 1s and 0s, and user-defined pattern from 3 to 32 bits length. While at Rx configuration these patterns are used to verify the incoming BERT pattern. Pattern Sync is achieved only if BERT pattern matches configuration options, configurable header lengths and header information.
Traffic Rate: The Traffic Rate option supports Bandwidth Rate defined as:
* Percent with range starting from 1 to 100% of current bandwidth
* Cell Ratio, where users can set the amount of ATM traffic cells and idle cells
Impairments: ATM BERT allows users to insert single bit error or a random error rate from 10-2 to 10-9 into the outgoing (TX) BERT cell stream.
Results: BERT Results are displayed in 2 ways - BERT Results with LEDs and Statistics. LEDs give users a quick way of viewing the test status. The three Status LEDs reflect current as well as history status. These LEDs indicate the Traffic status (whether traffic is being received or not), Pat Sync status (In Sync or Sync Loss) and Bit Error Status (whether bit errors are present).
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|Date:||Jan 19, 2011|
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