Printer Friendly

FPGA implementation of Simon Cipher for wireless sensor node.

INTRODUCTION

A wireless sensor network (WSN) is a network formed by a large number of sensor nodes where each node is equipped with a sensor to detect physical phenomena such as light, heat, pressure, etc. WSNs are regarded as a revolutionary information gathering method to build the information and communication system which will greatly improve the reliability and efficiency of infrastructure systems. Due to the increasing need for optimization of area, power, speed and the need for securing the information brings about the demand for real time implementation of simple cryptographic algorithms that will be robust, faster as well as power efficient Light weight cryptographic algorithm is essential for secure communication in the case of wireless sensor node. FPGA serves as a better alternative to ASIC due to the reprogramming property, which make them suitable for a wide variety of application [1].

Simon cipher [3] provides flexible hardware architecture for FPGA implementation still preserving the compactness of the algorithm, thereby standing as an impressive alternative of AES for resource constrained platform. Each instance of Simon uses the familiar Feistel rule of motion. The algorithm is engineered to be extremely small in hardware and easy to serialize at various levels. Simon cipher enables adaptive security by using variable key size moreover it also reduces the complexity of encrypting slightly longer message by incorporating variable block size.

I. Simon Cipher:

A. Encryption process:

Encryption is one of the main processes in any cryptographic algorithm. This involves the conversion of plain text in to cipher text by using key. The system can increase the security of 32 to 128 bits by providing a flexible key generation mechanism which can be used from toy settings to highly profile application. The encryption process in a Simon cipher involves two process which is the round function and key generation module implementation. The table 1.1 shown below illustrates the available key and block sizes in Simon cipher and the number of rounds it runs to maintain the level of security.

B. Round function implementation:

The round function implementation for all configuration of Simon involves [X.sup.1+1] and [X.sup.i] holding the upper and lower words of the block each of size n. these two words hold the initial input plain text, whereas [X.sup.i+2] holds the output after the initial round is executed. This implementation essentially consist of three functions viz. bitwise AND, bitwise XOR and circular shift operation. In each round, shifting and bitwise AND operation are performed on the upper word and it is XOR with the lower word which is in turn XOR'ed with the round key. The resulting output is given as the upper word for the next round and the upper word of the previous round becomes the lower word of the next round. The number of rounds is decided by the block and key sizes chosen.

Simon cipher essentially takes a key and generates T keys, where T is the number of rounds the round function block needs to operate. The position at which the round function text was stored previously is overwritten with the new round function text after each round. The re-usage of memory location at each round results in reduced memory occupation. The figure 1.1 shown below depicts the round function implementation of Simon cipher.

A. Key generation module:

Simon block cipher requires a unique key for each round. The key is generated by the key expansion block shown in Fig. 1.2. The key expansion block can vary from normal toy application to a highly secured military application. A multiplexer can be use to choose the type of application for which the key needs to be generated, where m denotes the splitting of the input key to generate the output key. As the value of m increases the security level also increases. For eg. a input of size 64 bit can have 2 key generation module each of key size 96 and 128 bit were in 128 bit is used for highly secure application. The key expansion module involves the bitwise AND, bitwise XOR, and circular shift operation. The AND function used at each round introduces non-linearity at each round. [K.sup.i+m] denotes the upper word and [K.sup.i] denote the lower word of the input key and size of m is a function of input key size. After each expansion operation, the round words are rotated right and the first round word is discarded and the last round word is replaced by the newly generated round key. The discarded round word of a particular round is used as the key for the round function. In addition the key schedule employs a constant

[FIGURE 1 OMITTED]

[C.sup.j] which essentially takes the value from n, where n is the word size parameter. [C.sub.j]=[2.sup.n]-4. Key expansion block essentially work like, the most significant word is XOR'ed is shifted right three and four times and XOR'ed with the least significant bit. In the case when m=4 there is an extra step the most significant word [k.sup.i+3] is circular shifted right by 3 and XOR'ed with [X.sup.i+1], circular shifted to the right by 1 and XOR'ed with the constant [C.sup.j.] as [k.sup.i] is the key used in the present round it will no longer be needed and is overwritten in every round.

II. Bit Serial Implementation:

When implementing a cipher in hardware the main thing that needs to be taken in to consideration are preservation of area and power. The choice of parallelism for implementation of the algorithm degrades both area and the throughput. In the case of bit serial implementation unlike the parallel implementation executes only one input bit per clock cycle. It makes use of shift-registers in LUT as memory elements. In the case of parallelism one round is executed per clock cycle for a block size containing r rounds. It needs r parallel stages to execute the encryption function so we move to bit serial implementation to reduce the size of the gates being used in the design resulting in reduced area.

A. Round Function Implementation:

The round function implementation for all 10 types of block sizes and key sizes configuration remains the same. As the size of the block size increases the size of the memory element also increases. Depending on the block size the block will be split in to two equal halves FIFO1 and FIFO2 so with the increase in size the FIFO size also increases. Each group of FIFO is divided into different sub section connected with each other through multiplexer. The multiplexer is used to activate the FIFO depending on the size of block size. The most significant word is stored in the shift register. Shift registers are use to do the circular shift operation

[FIGURE 2 OMITTED]

Each FIFO consists of a 2*1 multiplexer at the input side of the FIFO this helps in activation of the subsection of the FIFO. The bits are serially shifted out one by one and the operations are eventually performed.

B. Key generation module:

The main difference in the key generation module is the dependence of FIFO on security configuration value m, where the security configuration value rages as 2, 3 and 4 depending on the type of security level needed for a particular application. The FIFO is activated using a 2*1 multiplexer depending on the type of security configuration used. The 2* multiplexer is connected to the input of FIFO when the input to the multiplexer is 0 the input is bypassed through the FIFO when the input to the multiplexer is 1 the input to the FIFO is connected to ground. FIFO unlike the previous configuration Is divided in to different subsection and the activation takes place.

III. Spartan 3e:

Spartan 3e is a family of FPGA designed to meet the need of high volume and cost sensitive consumer electronic application. The family is tending to offer high density of gates ranging from 1-1.6 million gates. Spartan 3e tend to reduce the cost per logic by increasing the number of logic per I/O. The Spartan 3e enhancement combined with the 90nm technology delivers more functionality with an increased bandwidth thereby setting new standard in programmable logic (FPGA) industries. New features tend to increase the system performance and also provide them with reduced cost; because of their exceptionally low cost they are ideally suited for a wide variety of applications.

Spartan 3e stands as a superior alternative for ASIC's. ASIC's are one time programmable designed to satisfy a specific application whereas FPGA's can be re-programmed and manually updating the system whenever needed. One time programmable FPGA are also available but the SRAM based FPGA are the most dominant type. FPGA programmability also allows design upgrade with no replacement of hardware, which is impossible in the case of an ASIC.

IV. Implementation And Result:

The proposed hardware architecture is implemented in Xilinx Spartan 3e. Simon cipher stands as one of the best alternative in the case of area. In the case of wireless sensor node where in area stands as one of the major constrain this stands before the other block cipher.

The adaptability feature helps in using the same hardware for both toy setting and military application just by increasing the size of key. Increase in the size of key will result in the increase in clock cycles. One of the attractive features of this cipher is the variable key and blocks size. Since the key whitening process is not present in this area is greatly reduced, this is because the whitening process adds up the extra hardware thereby increasing the area. It is seen that as the key size is increased, the level of security also increases

V. Conclusion And Future Work:

The SIMON algorithm was implemented and had a huge advantage for resource constrained devices like wireless sensor node where area stands as the major constrain. This can be attributed to the fact that the algorithm requires minimum area and power compared to the other cryptographic algorithms. The ability of using FPGA is that they can be re programmed which stands as one of the main reason for implementing this algorithm in FPGA for flexibility. It enjoys the compact hardware due to the elimination of whitening steps which increases the size of hardware.A further extension of this work will be towards decreasing the number of cycles needed for execution so that the throughput can be improved and an adaptive solution for security system. An adaptive security protocol, which can increase and decrease the security level depending on the type of application it is being used to meet the real time application.

Thus by employing further cryptanalysis and security evaluation the above mentioned possibilities can be evaluated and verified for further enhancement of the algorithm.

REFERENCES

[1.] Aria Shahverdi, Mostafa Taha, Thomas Eisenbarth, 2015. "Silent SIMON: a threshold implementation under 100 slices", Hardware Oriented Security and Trust (HOST), 5-72015.

[2.] Soheil Feizi.Arash Ahmadi,Ali Nemati, 2014. "A hardware implementation of SIMON cryptographic algorithm", International conference on computer and knowledge engineering,29-30: 245-250.

[3.] Ege Gulcan, Aydin Aysu and Patrick Schaumont, 2015. "A flexible and compact Hardware Architecture for the SIMON Block Cipher", computer science, 8898: 34-50.

[4.] Ray Beaulieu, Douglas Shors, Jason Smith, Stefan Treatman-Clark, Bryan Weeks, Louis Winger, 2013. "SIMON and SPECK Families of Light Weight Block Cipher", National Security Agency.

[5.] Paris kitsos, Nicholas Sklavos, Maria Parousi and Athanassios N. Skodras, 2012. "A comparative study of hardware architecture for light weight block ciphers", International Journal for Computer and Electrical Engineering (IJCEE), 38: 148-160.

[6.] Swamendujana, Jayebbayamik and Manaskumarmaititi, 2013. "Survey on lightweight block cipher", International Journal for Soft Computing and Engineering(IJSCE), ISSN: 223-2307, 3-5.

[7.] Yalla, P., J. Kaps, 2009. "Light Weight cryptography for FPGA", Reconfigurable Computing and FPGA's, Reconfig'09, 9-11, 225-230.

(1) Iniya Abinaya M. and (2) Thiruvenkataesan C.

(1) M.E VLSI Design, SSN College of Engineering, Chennai, Tamilnadu

(2) Associate professor, Department of ECE, SSN College of Engineering, Chennai, Tamilnadu

Received 25 April 2016; Accepted 28 May 2016; Available 5 June 2016

Address For Correspondence: Iniya Abinaya .M., M.E VLSI Design, SSN College of Engineering, Chennai, Tamilnadu
Table. I: Block and Key Sizes.

Block size   Key size

32           64
48           72,96
64           96,128
96           96,144
128          128,192,256

Table II: Parallel vs. Serial Implementation of Simon Cipher.

                                                  Number of
                                                   slices
Block and key size                                occupied     Speed

Parallel implementation (Block size-64 and key       150      3.02 ns
size-96)

Parallel implementation (Block size- 64 and          228      7.61 ns
flexible key size--64, 96 and 128)

Serial implementation of the algorithm, Block        88       2.34 ns
size-64 and key size-96
COPYRIGHT 2016 American-Eurasian Network for Scientific Information
No portion of this article can be reproduced without the express written permission from the copyright holder.
Copyright 2016 Gale, Cengage Learning. All rights reserved.

Article Details
Printer friendly Cite/link Email Feedback
Author:Iniya, Abinaya M.; C., Thiruvenkataesan
Publication:Advances in Natural and Applied Sciences
Date:Jun 15, 2016
Words:2139
Previous Article:Design of nanoscale memristive arrays for memory applications.
Next Article:Hybridization of model based and template based techniques for speech enhancement.
Topics:

Terms of use | Privacy policy | Copyright © 2019 Farlex, Inc. | Feedback | For webmasters