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FPGA based switching noise reduction technique for multiple input DC to DC converter using sigma delta modulation.


In the present scenario, the impact of renewable energy sources is more and hence the necessity of DC to DC converters is also very important. The converters which are using these multiple renewable sources encounter certain issues. The three main issues in converters are switching losses, electromagnetic interference (EMI) and harmonics. Many control strategies are available to reduce the EMI produced by the inductor during switching, but the spikes are not properly addressed in the existing technique. The abrupt change in voltage and current variation due to the action of inductor lead to more switching noises and needs to be reduced in order to increase the efficiency. The quality of the input DC signal also determines the impact of EMI in the switching converters. The conventional sinusoidal pulse width modulation (SPWM) uses constant switching frequency thereby the power spectrum of harmonics is strengthened near the switching frequency.

These harmonics spikes result in EMI, switching losses of MOSFETs and mechanical vibration. A method called Random PWM (RPWM) is used to spread the switching frequency by randomly varying the frequency and duty ratio, but it is somewhat complex to generate the random switching phenomenon. In order to overcome these issues, an alternate method called Sigma Delta Modulation (SDM) is proposed in this paper. The harmonics produced near the switching frequency is minimized by Sigma Delta Modulation technique. SDM has high resolution and is very simple both in hardware and software. It produces switching pulses without any additional ON/OFF computation thereby the complexity gets reduced. The switching pulses are randomly changed with constant frequency. The generated switching pulses are frequency division multiplexed in order to control multiple input DC to DC buck boost converter. The factors affecting the Simultaneous Switching Noise (SSN) are the rate of change of voltage dv/dt and rate of change of current di/dt. The dv/dt creates leakage current because of capacitor and di/dt creates voltage because of the presence of inductor in the converter and the multiple switches used in the input of converters. We need to address multiple input converters to reduce the switching loss, to increase the efficiency and to reduce the cost instead of single input converters. In most of the cases, pulse width modulation techniques are used in power converter circuits to reduce EMI, but the limitations of this technique are that the spectrum accumulated near the switching frequency and the additional harmonics are not reduced further.

Even numbers of techniques are used to reduce this effect but the current stress and the EMI is not reduced considerably. Some other method called RPWM is used to spread the signals. The difficulty in this technique is that the selection of random number and the duty cycle is limited. Space dither SDM (SDSDM) and time dither SDM (TDSDM) are used to reduce these harmonics. The combined SDSDM is applied to reduce the harmonics by spreading concept and standard deviation of the sampling process is calculated. The experimental set up is considered for a 50v single input DC buck converter with a power 100W and frequency 25kHz (Seo-Hyeong Kim, et al., 2009). A boost Dc to Dc converter is designed by using delta sigma modulator and dither technique to switch on duty reference signal in two stages. By doing this approach, the maximum noise amplitude is minimized (Atsushi Hirota, et al., 2011).

A DC to DC converter by delta sigma modulator by considering the order, oversampling ratio and input voltage was investigated. Spurious performance and the efficiency are described. By increasing the oversampling ratio, the noise is reduced. The simulation result shows the buck converter with second order system having input voltage greater than 0.5v,OSR=64 produces the duty cycle greater than 75% and input voltage 0.3v,OSR less than 32 produces the duty cycle 65% (Kamala Hariharan, et al., 2009). A DC to DC buck converter is designed for a 0.35pm CMOS process by sigma delta modulator to improve the efficiency and to reduce noise by taking dead time controller, Gate width controller and DCM controller and the efficiency is achieved to 93% with 30dB harmonic spike reduction. To reduce the low frequency noise, a second order SDM is presented (Cai Shujiang, et al., 2011). The noise present in the power supply, SMPS is eliminated by sigma delta modulator. The rms noise power is 75.85 mW. A multibit approach is applied at quantizer level to reduce the noise spikes and the results show the rms noise power for 2 bit controller is 3.75mW and for a 4 bit controller is 0.24 mW. Performance comparison is done for a normal PWM with 1bit, 2 bit and 4 bit SD controller by using the concept of fixed period and variable frequency controller. This method is best suited for multibit scheme at quantizer level conversion (Steven, K., Dunlap and Terri S. Fiez, 2004).

A multiple input DC to DC converter is designed and the effective duty ratio is the integer function of common duty ratio. Additionally, a proportional integral (PI) controller is used to regulate this MIC. It multiplexes the output of various sources into a common dc buses and frequency division is used. Experimental results show the switching operation for open loop and closed loop and stability is achieved in only one circuit. This method is extended for digital implementation also (Chimaobi, N., et al., 2012). Multiple techniques to reduce EMI in DC to DC converter are discussed like spread spectrum normal sine PWM, bifurcation and chaotic PWM techniques and the performance comparison is done and simulation is carried out by using MATLAB and the results on power spectrum are also described. The power spectra for chaotic spreading and random PWM techniques are -25 dB/Hz and -23.8-24.4 dB/Hz respectively and it is concluded that among the various other methods addressed in this paper these two methods give the best result to reduce the EMI (Laxman Solankee, et al., 2012).

A DC to DC buck converter is designed and implemented in the field programmable gate arrays(FPGA). This enables the high speed dynamic response and better programming flexibility without adding more passive components. The transition from linear to nonlinear is easily achieved at the switching frequency 100KHz. The PWM controller and the ADC are implemented in FPGA and the algorithm is flexible and written in VHDL (Micro Milanovic, et al., 2005). A multiple input converter with sharing single secondary windings for single primary windings corresponding to multiple inputs. Due to its construction the circuit is simple and easy to manufacture (Qin Wang, et al., 2011). Some set of rules are proposed for MIC by decomposing the converters into basic cells and two families are generated. One family of MIC all inputs can power and load simultaneously or individually. In the second family one source is allowed to transfer energy to load at a time. Based on the connection rules a synthesis of MIC has been presented (Yan Li, et al., 2010).

Multiple input converters have cost effective and flexible ways to connect more sources and feasible topologies are designed to expand single input converter into multiple input converter. Four rules are formed to identify MIC topology, and six topologies are designed and their behavior is verified with the simulations (Alexis Kwasinski, 2009). The static and the dynamic characteristics are analyzed for the MIC's and the purpose is to realize zero emission power generation system. A two input buck boost DC to DC converter is taken as prototype model to control the operation and three modes are defined. Mode I is tested under light load condition, in mode II the output voltage is regulated by optimum power point and in mode III the output power is zero. In all the modes, the input source is considered as solar cell (Hirofumi Matsuo, et al., 2004). A multiple input DC to DC converter is designed by using a fixed frequency switching technique for a common load and low part count. It describes the converter operation for both CCM and DCM and it does not address about the isolation, duty cycle limits and power sharing issues (Bryan, G., Dobbs and Patrick L. Chapman, 2003). Another literature for single input multiple output converter was addressed in which the outputs are at multiple voltage levels which can be used to drive different applications and produces high power conversion efficiency. A prototype SIMO converter with coupled inductor was designed with one power switch and maximum efficiency exceeds 95% and conversion efficiency of 91% is achieved. But this system is not suited for dc-ac multilevel inverters (Rong-Jong Wai and Kun-Huai Jheng, 2013).

A CT sigma delta modulator for extended range is described at ADC level and a third order AS modulator was designed. A low power multichannel applications had been considered for this analysis and the modulation was carried over ADC during conversion process. A comparison was performed with respect to different test algorithms and shows the importance of non idealities in terms of number of functions (Julian Garcia, Saul Rodriguez and Ana Rusu, 2013). The dynamic characteristics of multi input multi output(MIMO) converter topology was described for both CCM and DCM mode. Power budgeting was established between the input sources. It uses one inductor thereby the circuit complexity and the cost got reduced and it is capable of performing Buck and Boost mode operation. Three inputs and two outputs are considered for this DC to DC converter (Hamid Behjati and Ali Davoudi, 2013).

By considering quantizer levels and coefficients of noise system function, a sigma delta modulator was designed for multibit applications. This does not use any converters but employs SDM at quantization levels and also the stability of the modulators is analyzed. Simulation was done by using MATLAB and a comparison was performed for three levels and five level quantizer for different order (Jaswinder Lota, et al., 2014). A digital controller was designed for a buck converter at high switching frequency by means of predictive control technique. It calculates current and voltage variation and the simulations are carried out by using MATLAB. The output power for vertex II FPGA is calculated as 450-682mW and the performance is analyzed by closed loop (Bo Li, et al., 2012).

A time sharing multiple inputs converter was designed in which the switching noise can be reduced by active clamping method. A soft switching technique was employed to isolate the TS-MIC and various components stress was calculated. The efficiency of active clamping with BSS type III is higher than with BSS type IV and snubber BSS type III. The switching loss is also reduced for active clamping with BSS type III (Sheng-Yang Yu and Alexis Kwasinski, 2013). A low complexity discrete time delta sigma modulator was designed and the chips SNR is 74.32dB and distortion ratio 81dB is achieved.It consumes 94mW power from 1volt supply. It results wide bandwidth and high dynamic range. Thus this modulator was designed at analog to digital conversion stage and the active area is also calculated (Su-Hao Wu and Jieh-Tsorng Wu, 2013).

This paper proposes a multiple input DC to DC Buck Boost converter with a single control strategy by SDM technique. The paper is organized as follows. Chapter 2 gives the proposed work. The proposed multiple input DC to DC converter with SDM is addressed in chapter 3. Results and discussion are described in chapter 4 and finally conclusion is addressed in chapter 5.

2. Proposed work:

Fig 1 shows the block diagram of the proposed work. A DC to DC buck boost converter is designed and this converter can have multiple inputs. Here three inputs are considered for our analysis. SDM is provided in the feedback path of the system where a constant frequency pulses are generated and these pulses are divided into many switching pulses by Time Sharing Algorithm (TSA).Here each cycle is split into three in order to control three inputs of a converter. The detailed functionalities of SDM and TSA are described in the successive sections. The switching pulses at the output of SDM are given to the three inputs of the converter so that the converter produces less EMI, harmonics and switching losses near the switching frequency. The entire system is in a closed loop so that the efficiency of the converter is improved. The quality of the DC inputs applied at the input of the converter is also increased. The switches used at the inputs produce switching pulses in a short period thereby the switching losses are to be concentrated.

2.1. Sigma Delta Modulation:

A first order Sigma Delta Modulation (Atsushi Hirota, et al., 2011) for a power converter circuit is depicted in Fig 2. The analog input voltage is given to ADC at the bottom of the circuit in Fig 2 to produce digital output and this is given to delay in producing integrated signal. This signal is given to 1 bit quantizer to produce sum signal in digital form. The number of section is our choice with respect to the order of the system.

y(n) = x(n -1) + {e(n) -e(n -1)} (1)

Where x(n) is the input signal, e(n) is the quantization error signal and y(n)is the output signal.

y(n) = +1 if x(n) [greater than or equal to] [V.sub.ref] - 1 if x(n) < [V.sub.ref] (2)

Fig 3 shows the simplified discrete time model of SDM. It also gives the connection diagram of input and output in z domain along with the noise function N (z).The transfer function of noise function is derived below.

By taking Z transform of "(1)"

Y (z) = X (z) [z.sup.-1] + E (z) (1 - [z.sup.-1]) (3)

This y (n) is given to the input of a switch. By using this model, we can define two transfer functions. One is with respect to signal and another one is with respect to noise. That is (Seo-Hyeong Kim, et al., 2009)

Transfer function of signal,

[H.sub.sig] (z) = Y(z)/X(z) = [z.sup.-1] (4)

Transfer function of noise,

[H.sub.noise] (z) = Y(z)/E(z) = 1 - [z.sup.-1] (5)

In order to find out the frequency response of the system, put z = [e.sup.j[omega]Ts], where [T.sub.s] = 1/[f.sub.s] is the sampling period. Substitute z = [e.sup.j[omega]Ts] in "(4)", we get

[{[H.sub.sig] (z)} z=e.sup.j[omega]Ts] = [e.sup.-j[omega]Ts]

By Euler's rule, the above equation can be written as

{[H.sub.sig](z)} = cos [omega]Ts-jsin[omega]Ts

The magnitude response is given by

[absolute value of [H.sub.sig(z)]] = 1 (6)

Similarly "(5)" can be simplified as

[{[H.sub.noise](z) = Y(z)/E(z)} z=e.sup.j[omega]Ts] = 1 - [z.sup.-1] = 1 - [e.sup.-j[omega]Ts]

The above equation can be rearranged as


By Euler's rule

= [e.sup.-j[omega]Ts/2][[e.sup.j[omega]Ts/2]]


= [e.sup.-j[omega]Ts/2] 2Sin 2[pi]f/2[f.sub.s]

= [e.sup.-j[omega]Ts/2] 2Sin [pi]f/[f.sub.s]

The magnitude response is given by

[absolute value of [H.sub.noise(z)] = 2 [absolute value of Sin [pi]f/[f.sub.s]] (7)

2.2. Time Sharing Algorithm:

The proposed technique is to generate an N number of switching frequency from Common Switching Function (CSF) with a higher switching frequency. This can be achieved by Time Sharing algorithm by using JK flip-flop in toggle mode and logic gates. The number of flip-flop required to generate the switching pulses is based on

N = [2.sup.n] (8)

Where 'n' is the number of flip flop and 'N' is the number of switching frequencies. In order to simplify the circuit, the number of inputs are taken as three. Here we have considered 2 flip-flops. So that in total we can generate up to 4 switching pulses. Out of 4 switching pulses, three pulses are taken into consideration for our work and the 4th output is reserved for extending the inputs in future.

[summation]j = N = 4, [summation]I = M = 3 (9)

Where N is the total number of j switching pulses generated by time sharing concept and M is the total number of i inputs of the converter.

In Fig. 4, two JK flip-flops are used with two stages in toggle mode to generate 4 pulses. In the first stage, the single frequency is divided into two time slots and in the second stage again this two time slots are divided into four time slots. In a similar fashion, we can generate any number of pulses by adding the stages as per "(8)".Among the possible outputs 'N', only required number (M) which is equal to the number of inputs is taken and the share factor [beta] is given by (Chimaobi, N., et al., 2012)

[beta] = M/N (10)

which is always less than or equal to 1. For our case [beta] = 3/4 [less than or equal to] 1. The effective duty cycle is the multiple of share factor of CSF and the fundamental frequency is given by

f = [f.sub.CSF]/N (11)

[D.sub.eff] = [beta] [D.sub.CSF] (12)

2.3. Correlation between sampling period and switching frequency:

To analyze the behavior of harmonics in SDM, the variation of switching periods is tested. As per the Nyquist theorem, if the sampling frequency is larger than the input maximum frequency, then the frequency ratio of SDM with SPWM will be calculated if [f.sub.s] is equal to the carrier frequency of SPWM. The relationship is plotted for both DC input and AC input. For a DC input (Seo-Hyeong Kim, et al., 2009),

R = 1/2 - 1/2 m (13)

Where m is the modulation index

For a AC input,

R = 1/2 - 1/[pi] m (14)

To analyze the change in output switching period, the switching number per switching cycle is calculated. From "(13)"

The possible value of sampling number is given by

[n.sub.s] = integer (2/1 - [absolute value of x]) (15)

where x is the input at the starting point of switching cycle. If the input is zero, then the sampling number ns will be 2. If the input is larger than the sampling number will also be higher and the value will be increasing with increase in input value (x).

3. Proposed Multiple Input Buck Boost Converter with SDM:

Fig.5 illustrates SDM scheme for three inputs DC to DC converter by using TSA. Due to the multiple switching, the converter may experience excess harmonics and switching noise which will reduce the efficiency of the converter. To eliminate this issue, an SDM discussed earlier is introduced which reduces the issue related to harmonics and switching noises. This switching scheme further utilizes the Time Sharing Algorithm which a single PWM cycle is divided into equal periods according to the number of inputs. The split signal is given to the gate control of switching devices. To operate on a voltage control mode, the output of converter is taken as the feedback through an ADC to the PID controller which provides necessary control signal to maintain a set point voltage and tracked voltage. This operation is continued until the set point voltage is achieved. Here a first order SDM section is taken into consideration. The SDM uses an integrator and quantizer in the feedback path and makes the converter circuit in a closed loop manner. The output of quantizer is +1 or -1 and the difference between input and quantizer output results the quantization noise.

The output is feedback to the input of ADC where it is converted into digital form by comparing this with the reference voltage. This digital output is given to the input of PID controller where the digital implementation of PID controller is performed to produce the output.

We know that the analog PID controller equation is given by


Where K, [T.sub.1], [T.sub.D] are adjustable parameters of PID controller and e (t) is the error signal. Equation (16) can be rearranged as in digital representation of PID controller


Where k is the sample number

[T.sub.s] is the sampling period

[K.sub.P] is the gain of the proportional control

[K.sub.I] is the gain of the integral control

[K.sub.D] is the gain of the derivative control

U (k) is the output of controller

Equation (17) gives the output of digital PID controller and this output is given to the input of SDM.


Fig.6(a) shows the simulation result and Fig.6(b) shows the experimental result of input and output voltages of Buck Boost converter for equal input voltages. Here the three inputs [V.sub.1], [V.sub.2] and [V.sub.3] are set to 5V and the corresponding output voltage [V.sub.out] is 15 V. That is, this converter acts as a Boost converter for the designed output i5 V.

Fig.7(a) shows the simulation result and Fig.7(b) shows the experimental result of input and output voltages of Buck Boost converter for unequal inputs. The three inputs are [V.sub.1]=0V, [V.sub.2]=5V and [V.sub.3] = 10 V. The output voltage is 15 V and so it works as boost mode.

The input and the output voltages of simulation and experimental result are illustrated in Fig.8(a) and Fig.8(b) respectively. It is clear from the figure that the three inputs [V.sub.1] = [V.sub.2] = 0V and [V.sub.3] is 10V and the output voltage is 15 V. Here also the converter acts as boost mode.

Fig.9(a) shows the simulation result and Fig.9(b) shows the experimental result of input and the output voltages of Buck Boost converter for unequal inputs. Here [V.sub.1]=5V, [V.sub.2]=0V and [V.sub.3] is 20 V and the converter Output is 15 V. The converter acts as both buck and boost mode.

The frequency response of Sigma Delta Modulated PWM control is shown in Fig. 10(a) & (b) for theoretical and practical response respectively. It is clear from the plot that the spectrum is spreaded over the entire frequency range instead of concentrating near the switching frequency. Thus, the SDM reduces the switching noise by the factor of 0.02 dB/decade. From Fig.10(a) the noise reduces to 0dB near the 1kHz but in practical response (Fig10(b)) this noise is decreased to 0.02 dB/decade and the design is limited to the maximum of 400kHz. Since our inductor is designed up to this resonant frequency and hence the switching noise is decreased at this maximum frequency.

The switching pulses of our proposed system are illustrated in Fig. 11. It is obvious from the graph that the system requires to initiate the switching pulses is 375[micro]s. That is, the system which is ready to produce the switching pulses takes 375ps from the initial set up.

Fig.12 depicts the output of SDM in a separate form. It is clear from the graph that the pulses are not equal as the operation of sigma delta modulator. It was observed that the pulse width was not equal and it follows as per the random variation of SDM technique in a closed system.

Fig. 13 shows the experimental set up of our proposed system. This consists of three inputs driven by three MOSFET switches, buck boost DC to DC converter. The required SDM waveform is generated by Xilinx FPGA processor and is driven the power converter to control the output to reduce the SSN.

Fig.14 depicts the frequency splitting action of PID controller. Here the single pulse between 200 and 600ps is split into three pulses as shown in the bottom Fig.14. This cycle is periodic and is repeated for every pulse.


In this paper, the reduction of switching noise for a multiple input DC to DC Buck Boost converter with a control strategy of Sigma Delta Modulation (SDM) is proposed. The FPGA generates SDM control PWM and the harmonics spikes is reduced near the switching frequency in a tremendous manner. This proposed research examines the converters by using simulation in buck boost mode. It is validated via experimental result for a three input configuration. A Sigma Delta Modulator is implemented by using an FPGA processor and the noise is evaluated for a prototype model corresponding to various input voltage combinations. The FFT analyses are also performed and the simulation and experimental results show that maximum of 0.02dB/decade noise reduction is achieved. This work uses several inputs and high clock frequency for further enhancement to reduce the switching noise.


Article history:

Received 1 June 2015

Accepted 28 June 2015

Available online 22 July 2015


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(1) Sasi.G and (2) Rajamani.V

(1) Department of Electronics and Communication Engineering, Fatima Michael College of Engineering and Technology, Senkottai Village, Madurai to Sivagangai main road, Madurai -625 020, Tamilnadu, India.

(2) Department of Electronics and Communication Engineering, Veltech Multitech Dr.Rangarajan Dr.Sakunthala Engg College, Chennai-600062,Tamilnadu India.

Corresponding Author: Sasi.G, Department of Electronics and Communication Engineering, Fatima Michael College of Engineering and Technology, Senkottai Village, Madurai to Sivagangai main road, Madurai -625 020, Tamilnadu, India.

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Title Annotation:field programmable gate array
Author:Sasi, G.; Rajamani, V.
Publication:Advances in Natural and Applied Sciences
Article Type:Report
Date:Jul 1, 2015
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