Estimating power amplifier large signal gain.
Microwave power amplifier large signal gain is determined by calculating the input power needed to produce a given output power. Both closed-form solutions and a CAD-based solution are presented, all based on device DC I-V characteristics and small signal models. A practical power amplifier design procedure is given and used to design a 22 GHz permeable base transistor (PBT) power amplifier. Although the analysis and design results presented here are useful by themselves, they also are intended to be used in conjunction with other CAD and measurement techniques, such as harmonic balance and load pull, to arrive at a starting point. Device designers should find these results useful, allowing them to predict how changes in a device's parameters will affect its microwave power amplifier performance.
Given the variety of microwave nonlinear computer-aided design (CAD) programs available today, such as the time-domain program Spice [dagger] and the harmonic-balance programs, such as Libra [double dagger] and Microwave Harmonica(**), one might wonder of what use are the relatively simplistic, quasi-static results presented in this paper. Assuming that the device in question can be modeled adequately, these other more complex analysis programs should provide more accurate results. However, at the present time, these programs are relatively expensive, compared with linear analysis programs, and still not available to the majority of microwave engineers. Additionally, there is not a large data base of large signal models, and deriving an accurate large signal device model is a very time-consuming task. These nonlinear programs require considerably more computational horsepower and processing time than simple linear analysis programs. While useful for analysis, these numeric methods provide little insight needed for design. They provide specific results for a given device in a given circuit, but don't show general trends and relationships.
In contrast, the results presented in this paper are simpler, sacrificing some accuracy for speed, ease-of-use and insight. Being based on graphical techniques, they give a better picture of amplifier operation while requiring much fewer calculations. All that is needed is a device's DC I-V characteristics, a small signal model, and a linear CAD program.
The methods presented here are sufficient to design many power amplifiers without the need for any additional nonlinear CAD analysis. These results also can be used in load-pull measurements and empirical amplifier tuning.
The techniques presented here also provide a fast, simple method of obtaining a starting point for nonlinear optimization, much closer to the ultimate solution than would be obtained by small signal analysis or by celestial extraction, that is pulling numbers out of the air. The better the designer's first guess (initial value), the fewer parameters that are varied, and the more constrained the parameters are, the faster the optimization will converge to the optimum solution. While important for linear CAD optimization, a good first guess is even more important in nonlinear CAD, due to the order-of-magnitude increase in computation requirements.
Expressions for output power, efficiency, power dissipation and optimum load resistance results were derived in a previous article. These are essentially the textbook Class A and Class B power amplifier results for two different device types, constant or linear transconductance; and two different load circuits, resistive or tuned. Since no textbook known to the author covers more than just a few of the simplest cases,[1,2] the derivations in Reference 1 fill this void. All of these results were consolidated into three tables, for easy reference.
The section on large signal gain combines the output power calculation of Reference 1 with an input power calculation to come up with large signal gain. Although extended considerably, the basic idea for this method of gain calculation came from an unpublished paper. Analytical expression for input power in terms of the device parameters are derived, followed by a novel graphic/numeric method of calculating input power employing the device I-V characteristics in conjunction with a linear circuit analysis program, such as Super-Compact(* [dagger]). This graphic/numeric method is probably the most important contribution of this paper.
The last section pulls all of the pieces together into a straightforward power amplifier design procedure, similar to the one described by Pucel, and implicit in the paper by Cripps. This method has been used to design a variety of 22 GHz PBT power amplifiers (70 to 500 mW), with excellent correlation between predicted and measured responses. One such amplifier design is given as an example.
It should be pointed out that many of the derivations below assume a voltage-controlled device, such as a FET, PBT or HEMT, and would have to be modified to handle a current-controlled device, such as a bipolar transistor.
Large Signal Gain
Having derived an expression for output power and efficiency in Reference 1, the one essential performance parameter still needed is large signal gain G. Since large signal gain is the ratio of output power to input power, and since output power already has been estimated, all that remains to be done is to estimate the input power.
Input Power and Large Signal Gain Calculation
This problem is broken down into two parts, as shown in Figure 1. For a given load circuit ([Z.sub.L][n]), using the device's DC I-V curves and the quasi-static analysis, estimates of output power, drain efficiency and input control voltage swing ~V~ can be obtained, as shown in Figure 1a. V is defined as the voltage across [C.sub.gs] and at DC is equal to [V.sub.GS]. Having determined what ~V~ is necessary to produce the desired output waveforms, the device's small signal model, as shown in Figure 1b, is employed to determine just how much input power is required to produce ~V~. While this method provides a means to calculate large signal gain, it does not describe explicitly how to realize this gain in practice.
It's appropriate to justify some of the assumptions made. At what bias point should the small signal model of Figure 1b be derived? While many of the parameters of the model, such as [L.sub.s] and [r.sub.s], are independent of the bias voltage, other parameters such as [C.sub.gs] and [C.sub.gd], are somewhat sensitive to the amount of bias voltage and the parameter [g.sub.m] can be very sensitive to the voltage bias. Since [g.sub.m] is used here in the input power calculation (Figure 1b) but not in the calculation of the control voltage swing (~V~) (Figure 1a), it turns out that [g.sub.m]'s influence on this calculation is not very important. Counterintuitively, it turns out that to be conservative, in this large signal gain calculation the maximum small signal [g.sub.m] should be used. This is convenient, since most small signal models are derived at the maximum small signal gain bias point. In PBTs, this high gm bias point also corresponds to a point of high [C.sub.gs], since high [g.sub.m] s usually are obtained at high currents which, in turn, are obtained at zero or even slightly positive gate-to-source voltages.
An alternative approach might be to take some average component value, using either a simple time average, or using a state space average, as employed in power supply design. A third approach that has been used to get accurate results with FETs is to bias the device in the middle of its I-V characteristics, halfway up the load line for Class A operation. Small signal parameters obtained at this bias point lie somewhere between their minimum and maximum values. Obviously, trying to model a time-varying element with a fixed value will lead to some error. This approximation is the primary source of error in the methods presented below.
Three additional simplifying assumptions concerning the output circuit are made in this approach:
1) the device's internal current source sees [Z.sub.L] [n] directly across it for the purposes of constructing the load line (Figure 1a), [C.sub.ds] and any drain inductance have been absorbed into [Z.sub.L] [n];
2) the small signal output resistance ([r.sub.ds]) is ignored;
3) all of the device output power is delivered to the load.
The first assumption neglects the common lead inductance and resistance, [L.sub.s] and [r.sub.s], respectively, in the output circuit calculations, which although not strictly valid, has been found to be a reasonably accurate assumption due to the other, larger impedances involved. In contrast, these common lead impedances are included in the input power calculations, since at high frequencies, all of the other impedances in the input circuit are small. Additionally, in the input circuit, the common lead inductance is multiplied by a term proportional to the device [f.sub.T], thereby magnifying its effect on high speed devices. Turning to the second assumption, although no small signal output resistance ([r.sub.ds]) is included explicitly, as explained below it has not been neglected. The third assumption implies that any series output resistance ([r.sub.d]) is negligible, output power dissipated in the common lead resistance is also negligible, and that the device output impedance is matched perfectly. This third assumption is one of the reasons this method fails to predict the observed drop in output power that occurs at the higher operating frequencies.
The large signal gain calculation procedure has two steps. First, determine the device output power along with the magnitude of the control voltage ~V~ needed to produce the output waveforms (Figure 1a) based on a load line superimposed on the device static I-V curves. Then, calculate the input power [P.sub.in] needed to produce ~V~ across [C.sub.gs] (Figure 1b).
The first step is straightforward once the load-line is established, as discussed later in this paper.
[P.sub.in] can be calculated in a number of different ways, depending on the application and the accuracy needed. Although circuit designers may make use of closed-form expressions, increased accuracy and speed is obtained from a computer simulation. Three different input power calculations are presented below, from the simplest, least-accurate method to the most complex and most accurate. The first two methods derive closed-form expressions for [P.sub.in] based on equivalent circuits, while the third method determines [P.sub.in] using a linear CAD program, Super Compact, along with a simple formula.
Closed-Form Expressions for Input Power
The first and simplest method to calculate [P.sub.in] models the device input circuitry as a simple R-C network, as shown in Figure 2. It is the basis for the other more complex and accurate methods proposed below. From basic circuit theory, (1) [Mathematical Expression Omitted] (2) [Mathematical Expression Omitted]
Equation 2 shows some of the important dependencies that are present in all of the following results. In order to produce a given control voltage swing ~V~, as frequency is increased, input power also must be increased to make up for the shorting effect of [C.sub.gs]. The commonly observed 6 dB/octave gain rolloff is obvious from this expression, since [P.sub.in] is proportional to the square of the frequency. The effect of scaling a device also can be seen from this equation. If the device size is doubled, [C.sub.gs] will be doubled and [r.sub.i] halved, resulting in twice the input power requirement. Since doubling the device area also doubles [I.sub.max], the output power also will be doubled, leaving the large signal gain unchanged, as expected.
However, the above method is not very accurate. Using Equation 2 to estimate the large signal gain of a 22 GHz, Class A PBT amplifier resulted in an overly optimistic estimate of 17.9 dB, compared with a measured gain of only 6 dB. Clearly, this simple model is inadequate. By adding three more circuit elements, the common lead inductance [L.sub.s], common lead resistance [r.sub.s] and the controlled current source [g.sub.m] V, as shown in Figure 3, much better accuracy is attained. Using Equation 1 to calculate the input power for this circuit results in, (3) [Mathematical Expression Omitted]
This equation is the same as Equation 2, except for the addition of the last two terms that raise the input power required, and, therefore, lower the gain. For the 22 GHz PBT amplifier, Equation 3 results in a large signal gain estimate of 9.6 dB, which is much closer to the actual measured gain, but still several dB high. This result shows how important the common lead impedance is to a device's gain. Notice that the term multiplying [L.sub.s], [g.sub.m]/[C.sub.gs], is 2[Pi] [f.sub.T], so the effect of common lead inductance becomes more pronounced with higher frequency devices.
In order to make this model more complete, it would be advantageous to add the feedback capacitance [C.sub.gd] to the circuit of Figure 3. However, deriving a closed-form expression for [P.sub.in] for this circuit becomes a tedious algebraic exercise. The effect of adding [C.sub.gd] more easily can be assessed if the common lead impedances are neglected. This analysis has been done in Reference 7, but will not be repeated here since the CAD-based method presented here eliminates the need for it. This CAD-based method allows all of the device parasitics to be included simultaneously. Finding closed-form solutions when more than a few reactive components are present becomes a complex procedure. A computer is much better suited for this analysis task.
A Computer-Aided Method of Calculating the Input Power
Computation intensive nonlinear CAD programs that can analyze power amplifier circuits are available. The method described here is a simple yet reasonably accurate method of determining power amplifier input power [P.sub.in] using a linear CAD program. Combining these results with the output power estimates of Reference 1 gives a good approximation to large signal gain. Although Super Compact is used in the example, the method easily is adapted to other programs.
This method starts from Equation 1, repeated below for convenience, (1) [Mathematical Expression Omitted] [Z.sub.in] easily is found for a transistor input network using a linear CAD program. To determine [I.sub.in] and the control voltage V, Equation 1 can be written as, (4) [Mathematical Expression Omitted]
If a linear CAD program could be used to evaluate the transadmittance term (~[I.sub.in]~/~V~) above, a solution would be in hand. The version of Super Compact used for this analysis (Version 1.81) does not allow this term to be evaluated directly, but it can be used with the aid of an added ideal transformer, as shown in the circuit of Figure 4. This circuit is the full input-circuit of the transistor, including common lead inductance and resistance, and feedback capacitance, along with an ideal one-to-one transformer across the gate source capacitance. This transformer is needed to access the floating (relative to ground) control voltage V, since Super Compact requires that one terminal of every port be at ground potential. A two-port network is formed, with the ports as labeled. Although a transadmittance is needed for Equation 4, the two-port's Z-parameters, not Y-parameters should be employed, to avoid loading the circuit. This is understood by comparing the definition of Z-parameters to Y-parameters, (5) [Mathematical Expression Omitted] Since the relationship between [I.sub.1] ([I.sub.in]) and [V.sub.2] (V) is desired, only [Z.sub.21] or [Y.sub.12] could contain the needed information. By examining these definitions, it becomes clear that [Z.sub.21] is the parameter to use, (6) [Mathematical Expression Omitted] [Z.sub.21] is the ratio of [V.sub.2] to [I.sub.1] with an open circuit at port 2, that is no loading, whereas [Y.sub.12] is the ratio of [I.sub.1] to [V.sub.2] with a short circuit at port 1, that is severe loading.(8)
Returning to the input power calculation, Equation 4 can be rewritten in terms of the circuit's Z-parameters. Remember that port 2 for this calculation is across the ideal transformer, not across the device drain source terminals. (7) [Mathematical Expression Omitted]
After analyzing the circuit of Figure 4 with Super Compact, the user is required manually to plug the results ([Z.sub.11] and [Z.sub.21]) along with [~V~.sub.0-p], determined from the load line, into Equation 7 to get the input power. The result from Equation 7 combined with an output power estimate from Reference 1 can determine large signal gain. Using this method on the 22 GHz PBT amplifier results in a large signal gain estimate of 7.2 dB compared with the measured gain of 6 dB.
Effect of Small Signal Output Impedance on Large Signal Gain
One of the assumptions made was that the small signal output impedance [r.sub.ds] could be ignored. [r.sub.ds] was actually included implicitly in the above analysis. [r.sub.ds] has little effect on the device output power capability, but, as shown below, can degrade large signal gain significantly.
The RF output power of a device is proportional to the [Delta] I X [Delta] V product, as determined from the load line. If the output resistance [r.sub.ds] is reduced from infinity to a value comparable to the load resistance [R.sub.L], the output voltage and current swings will be reduced, reducing the output power. However, by increasing the amplitude and changing the DC offset of the gate voltage drive waveform, the original drain source voltage and current waveforms can be restored, restoring output power to its original value, as shown in Figure 5. A Class A amplifier with a constant gm device is assumed. For convenience, the device also is assumed to have a finite incremental output resistance [r.sub.ds] equal to the load resistance [R.sub.L]. The input control characteristic ([I.sub.DS] vs. [V.sub.GS]) is no longer a single curve, but now a family of curves, with [V.sub.DS] as a parameter.
First, assume that this device is driven with the standard Class A gate source drive waveform, labeled [r.sub.ds] = [infinity]. During the most positive portion of the gate voltage swing ([V.sub.GS] [approximately equal to] 0), the finite output impedance has little effect. In contrast, when the gate voltage swings down to [V.sub.P], instead of pinching off as in the infinite output impedance case, the device still allows a current flow of [I.sub.max]/2. Although not explicitly drawn in this figure, the drain source current and voltage swings both have been reduced by a factor of two, reducing the output power by 6 dB.
By doubling both the amplitude and DC offset of the original gate-driven waveform, resulting in the waveform labeled [r.sub.ds] = [R.sub.L], the original output voltage and current waveforms can be restored. The penalty is a 6 dB drop in gain, but at least the output power is now the same as in the infinite-[r.sub.ds] case. Note that the gate control characteristic in this case has half of its original slope, so the effective [g.sub.m] is half of what it was with [r.sub.ds] = [infinity]. By looking at the gate voltages along an amplifier load line, the required input control voltage swing ~V~ is immediately apparent. Any decrease in [r.sub.ds] manifests itself in an increase in the ~V~ needed to achieve the desired output waveforms, increasing the input power required, and decreasing the large signal gain.
Load-Line Selection and Matching Network Design
Selecting the load line is one of the most important steps in the design process. The load line determines output power and drain efficiency, and is a primary determinant of large signal gain. Selection of the output circuitry and the device bias point determines which load line is traversed.
Tables 2 and 3 of Reference 1 give the optimum load resistance [R.sub.Lopt] for the various device and amplifier types. While in half of the cases addressed in Reference 1, [R.sub.Lopt] = 2([V.sub.DD] - [V.sub.SAT])/[I.sub.max], in the remaining four cases, [R.sub.Lopt] is considerably different. This value of load resistance was selected to maximize the output power. Load resistances greater than [R.sub.Lopt] result in reduced current swing [Delta] I, while resistances, less than [R.sub.Lopt] result in reduced voltage swing [Delta] V.
From the discussion in Reference 1, it is clear that one end of all of the load lines should be at the point ([V.sub.SAT], [I.sub.max]). At this end of the load line, the device has large incremental gain due to the wide spacing between the device curves.(9) The other end of the load line will be on the x-axis (zero current); the exact location of this voltage intercept point depends on the supply voltage, the amplifier class and the device type, as shown in Figure 6.
Figure 7 shows the DC I-V curves for a different PBT, an 8 X 40 [micro] [m.sup.2] device from the wafer 2P23A, from the one used in the prior examples. Notice that the device curves are spaced far apart at low drain source voltage and high currents, but group much closer together for higher voltages and lower currents. For this example, [V.sub.DD] = 6 V was selected as a bias voltage as a reasonable compromise between output power, gain and dissipation. These load lines are only approximate, since the PBT is not really a constant [g.sub.m] or linear [g.sub.m] device. As can be seen in Figure 6, as long as tuned loads are used, the constant and linear [g.sub.m] device load lines begin and end at the same points, but have different shapes, straight or curved. As far as the gain analysis is concerned, this shape difference has little effect. What is important to know is how much gate control voltage swing ~V~ is needed to get the desired output waveforms. From Figure 7, for this PBT operating Class A, 0.9 V peak-to-peak (0.6 V to -0.3 V) is needed, while in Class B, 0.7 V zero-to-peak (0.6 V to - 0.1 V) is needed. Note that if the I-V curves were perfectly flat, the Class B amplifier would require twice the gate control voltage swing as the Class A amplifier.
Matching Network Design
A simple method of designing the matching networks needed to present the required [R.sub.Lopt] to the device output, and to deliver [P.sub.in] to the device input, as shown in Figure 8, is presented. Between the 50 ohm input signal generator and the device input is a lossless input matching network and a wirebond, or mesh, inductance [L.sub.g] as shown in Figure 8a. Similarly, between the device controlled current source and the 50 ohm load resistor is the device drain source capacitance [C.sub.ds], a bonding inductance [L.sub.d], and a lossless output matching network, as shown in Figure 8b. Since the input and output matching networks are assumed to be lossless, [P.sub.in] [double prime] = [P.sub.in] [prime] = [P.sub.in], and [P.sub.out] [double prime] = [P.sub.out] [prime] = [P.sub.out]. Thus, the matching networks and device parasitic elements perform lossless impedance transformations from the 50 ohm system to the internal device level.
The input matching network can be designed in the same manner as in a small signal amplifier, conjugate matching the device input impedance for maximum power transfer. The output matching is also similar to the small signal case, but instead of presenting the device's current source with a real impedance equal to [r.sub.ds], the output circuitry should present an impedance of [R.sub.Lopt]. The output matching network can be designed by starting with a fictitious resistance, equal to [R.sub.Lopt], in the device across the current source, and working backwards out towards the 50 ohm load.
This procedure is illustrated in Figure 9a for a 22 GHz, Class A, PBT amplifier (with the device of Figure 7). From Table 2 of Reference 1, [R.sub.Lopt] [approximately equal to] 2([V.sub.DD] - [V.sub.SAT]) [I.sub.max]. From the device I-V curves of Figure 7, [V.sub.SAT] [approximately equal to] 1.8 V, [I.sub.max] [approximately equal to] 120 mA, so at 6 V bias, [R.sub.Lopt] [approximately equal to] 2(6-1.8)/0.12 = 70 ohms. Starting at 70 ohms (point A), [C.sub.ds] moves the impedance along a constant conductance circle, followed by the series inductance [L.sub.d] that moves the impedance up the constant resistance circle to point B. A simple output matching network consisting of a series 50 ohm transmission line rotating the impedance around to the real axis (point C), and a quarter wave transformer bringing the impedance to 50 ohms (point D), completes the impedance matching procedure.
One important point neglected up until now is stability. As in the case of small signal amplifier design, stability circles can be calculated, and regions of instability can be avoided. Since the above procedure presents [R.sub.Lopt] to the device instead of [r.sub.ds], the device is not conjugate matched simultaneously, so even if the stability factor k is less than unity, the above method may still result in a stable solution.
No attempt was made to terminate the harmonics (44, 66, 88 GHz, etc.) in a short circuit, but due to the shorting effect of [C.sub.ds] at these high frequencies, a fairly low impedance is presented, as shown in Figure 9b for the second harmonic frequency. The higher order harmonic frequencies will see still lower impedances, as the susceptance of [C.sub.ds] increases with increasing frequency.
Large Signal Performance Estimation and Verification
From Table 2 of Reference 1, for the Class A PBT amplifier biased at 6 V, 60 mA, [Mathematical Expression Omitted]. If the PBT were a constant [g.sub.m] device, drain efficiency = [Eta.sub.D] = 0.5([V.sub.DD] - [V.sub.SAT]/[V.sub.DD] = 0.35, whereas if it were a linear [g.sub.m] device, [Eta.sub.DD] = 0.67([V.sub.DD] - [V.sub.SAT])/[V.sub.DD] = 0.47. Large signal gain was calculated using the linear CAD approach described earlier, using Super Compact to calculate the Z-parameters of the input-network/ideal transformer combination. From the load line of Figure 7, [~V~.sub.0-p] = 0.45, and from Super Compact, ~[Z.sub.21]~ = 3.36, Re[[Z.sub.11]] = 2.43. Using Equation 7, [P.sub.in] = 22 mW, so the amplifier has a large signal gain of 7.6 dB.
This amplifier was built using the output matching network of Figure 9a along with a simple circuit to conjugate match the input. Testing in the lab was performed on a large signal scalar network analyzer. Some slight fine-tuning was needed to peak up the response at 22 GHz, as would be expected given the imperfect return loss of the coaxial connectors and bias-tees used at these frequencies. Measured results compared quite favorably with the predicted values above. Biased at 6 V, 60 mA, with an input drive power level of 13.4 dBm, [P.sub.out] = 20.4 dBm, so G = 7 dB, and [Eta.sub.D] = 30.5 percent. In order to arrive at the predicted output power of 21 dBm, the input drive power level had to be increased to 14.2 dBm, resulting in a large signal gain of 6.8 dB and a drain efficiency of 35 percent. It should be noted that for a device with a high transconductance, determining [~V~.sub.0-p] accurately from the load line is important for precise gain predictions.
Several methods of large signal gain estimation have been presented, all based on input power calculations derived here along with output power estimates from a previous paper, Reference 1. Two simple, but inaccurate, closed-form expressions for input power were derived that give direct relationships between the various device parameters and the large signal gain. A method of calculating input power with the aid of device I-V characteristics, a small signal device model, and a linear CAD program was presented. Good correlation between estimated and measured performance was demonstrated.
A simple method of designing large signal amplifiers was presented and demonstrated on a 22 GHz PBT amplifier. This method can be used as a stand alone procedure for many power amplifier designs, or as a starting point in nonlinear CAD-based designs and load pull measurements.
One limitation of the above results is that they contain no mechanism for power rolloff with frequency, as is encountered frequently at the higher microwave and mm-wave frequencies. This limitation could be overcome by calculating the attenuation of the device internal current generator out to the device drain source terminals, including device series output resistance [r.sub.d], and common lead impedance ([r.sub.s] and [L.sub.s]). [Figures 1 to 9b Omitted]
(*)Invited paper. ([dagger])Spice originally was developed at the University of California, Berkeley. ([double dagger])Libra is a trademark of EEsof Inc. (**)Microwave Harmonica is a trademark of Compact Software.
(8)For the reader still convinced that [Y.sub.12] will not work, calculating the Z- and Y- parameters for the simple case of the R-C input network of Figure 2 shoulddo the trick. For this circuit, [Y.sub.12] = -1/[r.sub.i] while (1/[Z.sub.21]) = s [C.sub.gs]. Plugging these relationships into Equation 4 for the current/voltage ratio results in the correct input power expression (Equation 2) only if (1/[Z.sub.21] is used. (9)While this is true for the PBTs and most FETs, this may not be true for HEMTs that often have maximum I-V curve spacing at moderate currents.
L.J. Kushner, "Output Performance of Idealized Microwave Power Amplifiers," Microwave Journal, October 1989, pp. 103. H.L. Krauss, C.W. Bostian and F.H. Raab, Solid State Radio Engineering, John Wiley & Sons, 1980, Chapters 12 to 14. W.E. Courtney and A. Gopinath, "Efficiency of GaAs Power MESFETs," M.I.T. Lincoln Laboratory, internal memorandum. R.A. Pucel, "Monolithic Microwave Integrated Circuits," notes for lectures presented in course on Advanced Microwave Circuits Design, U.C.L.A. Extension, Oct. 1983, pp. 81-83. S.C. Cripps, "A Theory for the Prediction of GaAs FET Load-Pull Power Contours," 1983 IEEE MTT-S Digest, pp. 221-223. Middlebrook and Cuk, "A General Unified Approach to Modeling Switching-Converter Power Stages," 1976 IEEE PESC Record, pp. 18-34. L.J. Kushner, Microwave Power Amplifier Analysis and Design, Technical Report 812, Lincoln Laboratory, Massachusetts Institute of Technology, Dec. 16, 1988.
Lawrence J. Kushner received his BS degree from Purdue University in 1979 and his MS degree from the Massachusetts Institute of Technology in 1982, Kushner has been a staff member at the Lincoln Laboratory, MIT, where he has worked on transmitters, receivers and frequency synthesizers for EHF satellite ground terminals. Prior to that, he was a member of Bell Laboratories' technical staff. While in school, Kushner held various positions at the Mitre Corp., Hewlett-Packard and the C.S. Draper Laboratory.
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|Author:||Kushner, Lawrence J.|
|Date:||Jun 1, 1990|
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