Printer Friendly

Enhanced device and circuit-level performance benchmarking of graphene nanoribbon field-effect transistor against a nano-MOSFET with interconnects.

1. Introduction

The number of transistors on a typical 1 x 1cm chip has grown exponentially with twofold increase every 18 months keeping Moore's Law [1] on track. Serious hindrances are in sight as transistor scaling enters the nanometer domain. Short-channel effects are significant as devices are scaled below sub-100 nm, providing challenges and opportunities for device and process engineers. Researchers across the globe are exploring new nanomaterials with transformed architecture to circumvent the roadblocks of silicon-based nanotechnology for enhanced circuit performance. Interconnects also play a key role as channels reach nanometer scale and resistance surge takes on an increasing importance [2]. Carbon-based allotropes offer a distinct advantage in a variety of applications [3-8]. Graphene nanoribbons (GNRs) are one-dimensional (1D) nanostructures restricting carrier motion in only one direction, reducing scattering for enhanced mobility [6, 9]. The transistor current is quite high as electrons are injected from the source and transit to the drain terminal [6, 10-12]. A narrow width semiconducting GNR is utilized as a channel in a top-gated transistor [13-15]. This pushes the limits of complementary metal-oxide-semiconductor (CMOS) type of technology beyond its limits in a GNR. This paper focuses on modeling, simulation, and benchmarking of top-gated graphene nanoribbon field-effect transistors (GNRFETs) against MOSFET. In addition, the evaluation of logic performance is carried out for both devices. It is observed that there is a good agreement between GNRFET and MOSFET based on the drain current-voltage (I-V) characteristics. The energy-delay product (EDP) and power-delay product (PDP) are the performance metrics that represent the energy efficiencies of GNRFET and MOSFET logic gates. The simulations in this work are carried out for the 16 nm manufacturing processes. In the following, device model framework of our previous work [7, 16-19] is extended for the simulation and analysis of GNRFET and MOSFET at 16 nm node. Circuit-level models of GNRFET are benchmarked against MOSFET. Logic performances of carbon and silicon-based inverter and NAND and NOR gates are assessed. For a fair assessment, the same channel length, 1=16 nm, is adopted for GNRFET, PMOS, and NMOS. The device modeling is carried out in MATLAB and circuit development and simulation is performed using HSPICE and Cosmoscope.

2. Device Modeling

The simulated silicon MOSFET is based on Berkeley short-channel IGFET model (BSIM) which was the standard model for deep submicron CMOS circuit design in the early 2000s [20]. IC companies including Intel, IBM, AMD, National Semiconductor, and Samsung widely use the charge-based model as an electronic computer-aided design (ECAD) tool. BSIM4 version 4.7 MOSFET model is utilized in the simulation of NMOS and PMOS [21] in the present assessment. The top view of GNRFET with source and drain contacts is depicted in Figure 1.Variousvaluesof and (see Figure 2) are given in Table 1.

3. Proposed Layout and Design

The interpolated contact size C and spacer size S of 16 nm node process technology are illustrated in Figures 2(a) and 2(b), respectively.

The channel width, W, is a function of C and S as given by

W = C + 2S. (1)

Table 1 gives design specifications for channel lengths from 16 to 180 nm range.

4. Analytical Modeling of GNRFET

In this section, the analytical model of GNRFET is derived. The channel surface potential [V.sub.SC], or self-consistent voltage as is commonly known, is solved numerically in MATLAB using Newton-Raphson algorithm to obtain the voltage potential at the top barrier along the channel [23]. The VSC is given by

[V.sub.SC] = [V.sub.L] + [V.sub.p] = -[Q.sub.t] + [DELTA]Q/[C.sub.[SIGMA]] (2)

where [C.sub.[SIGMA]] is the total sum of capacitance at all the four terminals and [Q.sub.t] is the total charge. [DELTA]Q is the additional charge due to the increase of [V.sub.SC]. [V.sub.L] is the potential appearing across the channel region and [V.sub.P] is existing across the parasitic regions. The other symbols in (2) are given as follows where Ns is the density of positive velocity states, [N.sub.d] is the density of negative velocity states and [N.sub.0] is the electron density at equilibrium:


The carriers obey the Fermi-Dirac probability distribution as follows:


where [U.sub.SF] and [U.sub.DF] are defined as

[U.sub.SF] = [E.sub.F] - q[V.sub.SC], [U.sub.DF] = [E.sub.F] - q[V.sub.SC] - q[V.sub.d]. (5)

The one-dimensional (1D) density of state (DOS) function in (4) is defined as

D(E) = 2[g.sub.v][g.sub.s]/3[pi][]t [summation over (i)] E/[square root of ([E.sup.2] - [(EG/2).sup.2])], (6)

where [] = 0.142 nm is the C-C bond length and t = 3 eV is the C-C bonding energy. In (6), [E.sub.G] is the bandgap energy, gs is the spin degeneracy, and [g.sup.v] is the valley degeneracy. In an armchair GNR (aGNR), [g.sub.v] = 1. A nonlinear regression model of [V.sub.SC] is obtained through the use of the polynomial fit [24,25]. The nonlinear approximation for [V.sub.SC] dependence on [V.sub.d] and [V.sub.g] in the form of fifth-order polynomial is given to replace the Newton-Raphson algorithm in (2). The regression model is given as

[V.sub.SC]([V.sub.g], [V.sub.d]) = A[V.sub.d] + B[V.sub.g.sup.5] + C[V.sub.g.sup.4] + D[V.sub.g.sup.3] + E[V.sub.g.sup.2] + F[V.sub.g] + G, (7)

where A, B, C, D, E, F, and G are the coefficients extracted from MATLAB curve fitting tool.

The coefficients A to G in Table 2 are empirical parameters used for curve fitting (2).

HSPICE utilizes (8) to simulate the drain and gate I-V characteristic of GNRFET and MOSFET. The noniterative model allows cross-platform simulation, shorter execution time, and reduced computational cost [26]. In GNRFET, when gate and drain voltages are applied, [V.sub.SC] is reduced by [V.sub.L]. This would result in a flow of electron in the channel that increases [V.sub.SC] by [V.sub.P] due to introduction of the additional charges [27]. In the [I.sub.d]-[V.sub.d] simulation of GNRFET, the [I.sub.d]-[V.sub.d] equation can be written in [V.sub.d], [V.sub.s] and [V.sub.g] coefficients as given by


where [G.sub.ON] is the on-conductance.

5. Device Simulation

The device performance of GNRFET and MOSFET are compared by evaluating their respective [I.sub.d]-[V.sub.d] characteristic as shown in Figure 3. The output response of p-type and n-type MOSFETs is superimposed for comparison purposes. Also, the [I.sub.d]-[V.sub.d] characteristics of p-type and n-type GNRFETs are symmetrical as in a CMOS and thus coincide with each other. Figure 4 illustrated the [I.sub.d]-[V.sub.g] transfer characteristic of n-type and p-type MOSFET and GNRFET. DIBL and SS are calculated from the [I.sub.d]-[V.sub.g] curveand are given as

DIBL = [partial derivative][V.sub.T]/[partial derivative][V.sub.d], SS = [partial derivative][V.sub.g]/[partial derivative]([log.sub.10][I.sub.d]). (9)

The range of the DIBL measurement is taken between [absolute value of ([V.sub.d])] = 0.1 V and [absolute value of ([V.sub.d])] = 1 V and the SS measurement is for the drain current curve at [absolute value of ([V.sub.d])] = 0.1 V. As deduced from Figure 3, GNRFET has a lower linear on-conductance compared to MOSFET. In addition, GNRFET achieves higher saturation current values than those of MOSFET for most gate voltages.

As listed in Table 3, the DIBL of MOSFET is better than GNRFET. The subthreshold swing (SS) of both devices is comparable. The [I.sub.on]/[] ratio of GNRFET is two-order magnitude lower than that of MOSFET. This is due to a lower linear on-conductance limit of a ballistic GNRFET. The on-conductance limit, GON, with zero contact resistance is given by

[G.sub.ON] = 2[q.sup.2]/h, (10)

where q is the electronic charge and h is Planck's constant. The simulation is carried out using a high gate dielectric constant (high-k) with high thermal stability. In a practical microfabrication, zirconium dioxide which has high-k values between 20 and 25 is considered [28].

Note that different values of oxide thickness are being used to obtain almost symmetrical I-V characteristics for both p-type and n-type MOSFET, namely, in the linear region. It is found that when all the transistors adopt equal oxide thickness, the maximum current at [V.sub.d] =1 V and [V.sub.g] = 1 V differs from one another. The output waveform will not have uniform square wave anymore. The propagation delay, rise time, and fall time will be significantly affected. Thus, they are no longer suitable for logic application due to the mismatch of the p-type and n-type [I.sub.d]-[V.sub.d] curves at the voltage transfer characteristics.

6. Circuit Design

In this Section, circuit simulation is considered. As part of the circuit design process, parasitic capacitance, namely, load capacitance [C.sub.L] is determined for an accurate circuit representation. The top diagram in Figure 5 shows a typical arrangement of two inverters in series with CL. The components of CL are gate-drain capacitance [C.sub.gd1], [C.sub.gd2], drain-bulk capacitance [C.sub.db1], [C.sub.db2], and wire capacitance [C.sub.W] as depicted in the bottom diagram of Figure 5. Note that the term wire capacitance is used interchangeably with interconnect capacitance. Table 4 lists the local, intermediate, and global copper and GNRFET interconnect capacitances for 32 nm, 22 nm, and 14 nm technology process. The finite element method (FEM) charts the pathways in obtaining capacitances as in [29]. The interconnects used in the simulation are considered to be in the intermediate layer [30] and vary from 1 [micro]m to 100 [micro]m in length [31]. It is found that for 0.18 [micro]m technology, average interconnect lengths are considered to be 7 [micro]m per fan-out [31]. These interconnect specifications from ITRS 2005 are shown in Table 4.

Table 5 shows the extrapolated interconnect capacitances for the 90 nm, 65 nm, 45 nm, and 16 nm process technologies. The capacitance values of copper and metallic GNR are extrapolated from Figure 6 using a linear function based on the intermediate capacitance in Table 4.

Table 6 contains the relevant equations for the load and output capacitance for the logic gates.

7. Performance Analysis of Digital Circuit

HSPICE is used to simulate the logic operations of GNR-FET and MOSFET. The schematic diagram and input-output waveforms of GNRFET and MOSFET NOT, two-input NAND (NAND2), two-input NOR (NOR2), three-input NAND (NAND3), and three-input NOR (NOR3) gates are delineated in Figures 7, 8, 9, 10, and 11, respectively. All the logic gates consist of 1 [micro]m copper interconnects at the output terminals. In the simulation, the maximum fan-in for a gate is limited to 3. Correct logical operations are confirmed from the simulation results as shown in the input-output waveforms. Voltage spikes observed are found to be negligible in the output waveform of MOSFET in Figures 7(b)-11(b). The circuit inductance possibly causes spikes that are possible to be compensated by incorporating an on-chip decoupling capacitor at the output in parallel. Note that Figures 7-Figure 11 are important to calculate the propagation delay which is computed between 50% of the input rising to the 50% of the output rising. Together with the average power consumption, the metric performance of logicgates in term of EDP and PDP is obtained. PDP and EDP parameters are the figure of merit for logic devices. PDP and EDP are given by

PDP = [P.sub.av] x [t.sub.p], EDP = PDP x [t.sub.p], (11)

where [P.sub.av] is the average power and [t.sub.p] is the propagation delay. Table 7 lists the [P.sub.av] and [t.sub.p] for various logic gates as obtained from the simulation. The PDP and EDP for GNRFET are an order of lower magnitude compared to MOSFET due to smaller [t.sub.p] and its ultralow [P.sub.av] during logic operation as revealed in Table 7. GNRFET power consumption is by at least 1 order of magnitude lower than that of a MOSFET.

Figure 12 depicts the layout for GNRFET NOR2 schematic shown in Figure 9(a). In the top-gated design, the GNR is placed under the metal gate and thus hidden from the view. The [V.sub.g] is supplied to the device through terminals A and B. The vertical-interconnect-access (via) as labeled in Figure 12 allows a conductive connection between different layers. Torealize the number of p-type and n-type transistors as given in Figure 9(a), three and four electrode contacts, respectively, are implemented in the layout. While the series configuration of the p-type transistors requires only three electrode contacts, and four electrode contacts are needed for the n-type transistors connected in parallel.

The Fermi velocity in a GNRFET is distinctly higher than that in a heavily doped MOSFET. Obviously, degenerate statistics is applicable in heavily doped channels. The intrinsic velocity for a nondegenerate low-doping level is limited to the thermal velocity which is lower than the Fermi velocity in heavily doped semiconductors. The device modeling of GNR adopts similar modeling framework in [17] where we have modified the density of states and quantum conductance limit of a ballistic SWCNT to GNR. The maximum drain current for a monolayer GNRFET is found to be at 19 [micro]A. For CNTFET, the maximum drain current is at 46 [micro]A. Never the-less, both low dimensional carbon devices outperform silicon MOSFET in term of power-delay-product (PDP) and energy-delay-product (EDP) by at least one order of magnitude.

Figure 13 depicts the GNRFET PDP and EDP, respectively, for 0-100 [micro]m copper interconnects in length for various logic gates. Figure 14 shows the MOSFET PDP and EDP, respectively, for 0-100 [micro]m copper interconnect in length for various logic gates. The logic gates with high fan-in exhibit increased EDP and PDP as exhibited by these plots. The cutoff frequency at which the current gain is 1 is used to describe the high-frequency performance of a transistor. The current unity gain cutoff frequency of the intrinsic transistor [32, 33] with interconnect capacitance is given by

[f.sub.T] = 1/2[pi] [g.sub.m]/[C.sub.g] + [C.sub.L] + [C.sub.sub], (12)

where Cg is the gate capacitance, CL is the load capacitance, and Csub is the substrate capacitance. Devices with thicker substrate insulator (for instances, 500 nm) and smaller contact area have higher unity cutoff frequency. The unity current gain cutoff frequency for GNRFET circuit model is depicted in Figure 15. The model uses a copper interconnect of the 16 nm, 45 nm, 65 nm, 9 and 0 nm nodes technology. The simulation shows that a 16 nm GNRFET can deliver a unity cutoff frequency of 400 GHz. The interconnect length varies from 0.01 [micro]m to 100 [micro]m. It is found that cutoff frequency is inversely proportional to interconnect length. When the interconnects are longer than 10 [micro]m, the frequency remains the same regardless of the technology nodes. Therefore, it is essential to utilize interconnects as short as possible to tap the high-frequency capability of the CNTFETs [17] and GNRFETs. Our finding is consistent with the state-of-the-art graphene transistors that have been shown to reach operating frequencies up to 300 GHz experimentally [34].

8. Conclusions

Complementary CMOS based on -type and -type MOS-FETs has been at the center stage in industrial environments because of low power consumption. A CMOS circuit draws power from the source only when an inverter is switching from low to high or vice versa. A CMOS inverter is a building block for other gates to build a complete ultralarge-scale-integrated (ULSI) ensemble. After the 2010 Nobel Prize awarded to graphene, graphene allotropes have overwhelmed the center stage to capture the advantage of More than Moore's Era. In fact, Arora and Bhattacharyya [35] show that CNT band structure can be drawn from that of graphene nanolayer with rollover in various chirality directions. GNR [36] offers similar endless opportunities. Considering these noteworthy developments, we believe that graphene allotropes offer distinct advantage over and above the CMOS architecture for a variety of applications in creating sensors, actuators, and transistors for implementation in the ULSI. As graphene allotropes bring to focus the advanced applications, we consider GNR as an example to demonstrate its superiority over the CMOS. Primary reason why graphene is superior to silicon is its intrinsic velocity. The drift in graphene is limited to the Fermi velocity [v.sub.F] [approximately equal to] [10.sup.6] m/s that is 10 times than that of a silicon ([v.sub.i] ~ [10.sup.5] m/s). Saturation velocity limited to the intrinsic velocity vi determines the high-frequency cutoff of a ULSI circuit. That is the reason that graphene-based electronics will offer unique advantage in high-frequency circuit design. As current saturates, the power in a ULSI circuit is governed by P = VIsat and hence becomes a linear function of voltage, in direct contrast to square law dictated by Ohm's law. The power consumption will be much lower in a graphene circuit affording the opportunity to lower the scale of the voltage source. Power-frequency product is a figure of merit in ULSI applications. The paper shows distinct advantages of graphene-based integration in ULSI circuits in designing various Boolean gates. The comparative study stretches the landscape of More than Moore era as traditional scaling reaches its limit. As demonstrated by Greenberg and del Alamo [37], interconnect degrades the device behavior. That is why it is important to include interconnects in the total package of these studies. The rise in the resistance in scaled-down channels also affects the voltage divider and current divider principles, normally based on Ohm's law. When interconnects are considered in series with the channel, the resistance surges for a smaller length resistor, creating the importance of comprehensive study [38]. Similarly, when parasitic channels are considered in parallel with the conducting channel, the resistance can be higher than what is predicted from Ohm's law. This rise in resistance can increase the RC time constants as demonstrated in [38, 39]. GNRFET with proper architecture can extend the domain of More than Moore era in meeting the requirements of the future. Short-channel effects that restrict the silicon technology to reach its full potential are controllable in GNRFET architecture. GNRFET has shown comparable device performance against 16 nm CMOS node. In terms of circuit performance in logic design, the PDP and EPD of GNRFET are distinctly better. The modern adage is "silicon comes from geology, but carbon comes from biology." This transformation from silicon to carbon-based graphene will usher new era for circuit design based on carbon electronics that is expected to be compatible with bioelements. ULSI designers will greatly benefit from this comparative study as they change their mode of thinking from CMOS to new graphene-based ULSI. We are also expecting that parasitic elements that inhibit the speed of ULSI circuits will pose less of a problem in future architectures based on our findings. The all-encompassing landscape covered in this paper will find broader applications benefitting not only the research labs in their characterization and performance evaluation, but also in giving new directions to the industry in product development that will benefit global community.

Conflict of Interests

The authors declare that there is no conflict of interests regarding the publication of this paper.


The authors would like to acknowledge the financial support from UTM GUP Research Grant (Vote nos.: Q.J130000.2523.04H32 and Q.J130000.2623.09J21) and Fundamental Research Grant Scheme (FRGS) (Vote nos.: R.J130000.7823.4F247, R.J130000.7823.4F273, and R.J130000.7823.4F314) of the Ministry of Higher Education (MOHE), Malaysia. Weng Soon Wong thanks Yayasan Sime Darby (YSD) for the scholarship given for his study at the Universiti Teknologi Malaysia (UTM). Vijay K. Arora appreciates the Distinguished Visiting Professorship of the UTM. UTM Research Management Centre (RMC) provided excellent support conduciveness to the research environment needed to complete project of this magnitude with personnel of far-reaching background.


[1] C. A. MacK, "Fifty years of Moore's law," IEEE Transactions on Semiconductor Manufacturing, vol. 24, no. 2, pp. 202-207, 2011.

[2] T. Saxena, D. C. Y. Chek, M. L. P. Tan, and V. K. Arora, "Microcircuit modeling and simulation beyond Ohm's law," IEEE Transactions on Education, vol. 54, no. 1, pp. 34-40, 2011.

[3] V. K. Arora, "Quantum transport in nanowires and nanographene," in Proceedings of the 28th International Conference on Microelectronics (MIEL '12), Nis, Serbia, 2012.

[4] V. K. Arora, D. C. Y. Chek, M. L. P. Tan, and A. M. Hashim, "Transition of equilibrium stochastic to unidirectional velocity vectors in a nanowire subjected to a towering electric field," Journal of Applied Physics, vol. 108, no. 11, Article ID114314, 2010.

[5] R. Vidhi, M. L. P. Tan, T. Saxena, A. M. Hashim, and V. K. Arora, "The drift response to a high-electric-field in carbon nanotubes," Current Nanoscience, vol. 6, no. 5, pp. 492-495, 2010.

[6] V. K. Arora, M. L. P. Tan, and C. Gupta, "High-field transport in a graphene nanolayer," Journal of Applied Physics, vol. 112, Article ID 114330, 2012.

[7] M. L. P. Tan, "Long channel carbon nanotube as an alternative to nanoscale silicon channels in scaled MOSFETs," Journal of Nanomaterials, vol. 2013, Article ID 8312521, 5 pages, 2013.

[8] A. Pourasl, M. T. Ahmadi, M. Rahmani et al., "Analytical modeling of glucose biosensors based on carbon nanotubes," Nanoscale Research Letters, vol. 9, article 33, 2014.

[9] V. K. Arora, "Theory of scattering-limited and ballistic mobility and saturation velocity in low-dimensional nanostructures," Current Nanoscience, vol. 5, no. 2, pp. 227-231, 2009.

[10] H. Xu, "The logical choice for electronics?" Nature Materials, vol. 4, no. 9, pp. 649-650, 2005.

[11] A. Raychowdhury and K. Roy, "Carbon nanotube electronics: design of high-performance and low-power digital circuits," IEEE Transactions on Circuits and Systems I, vol. 54, no. 11, pp. 2391-2401, 2007.

[12] M. L. P. Tan and G. A. J. Amaratunga, "Performance prediction of graphene nanoribbon and carbon nanotube transistors," in Proceedings of the International Conference on Enabling Science and Nanotechnology (EsciNano '10), vol. 1341 of AIP Conference Proceedings, pp. 365-369, December 2010.

[13] L. Liao, J. Bai, R. Cheng et al., "Top-gated graphene nanoribbon transistors with ultrathin high-[kappa] dielectrics," Nano Letters, vol. 10, no. 5, pp. 1917-1921, 2010.

[14] G. S. Kliros, "Gate capacitance modeling and width-dependent performance of graphene nanoribbon transistors," Microelectronic Engineering, vol. 112, pp. 220-226, 2013.

[15] W. Wang, X. Yang, N. Li, L. Zhang, T. Zhang, and G. Yue, "Numerical study on the performance metrics of lightly doped drain and source graphene nanoribbon field effect transistors with double-material-gate," Superlattices and Microstructures, vol. 64, pp. 227-236, 2013.

[16] D. C. Y. Chek, M. L. P. Tan, M. T. Ahmadi, R. Ismail, and V. K. Arora, "Analytical modeling of high performance single-walled carbon nanotube field-effect-transistor," Microelectronics Journal, vol. 41, no. 9, pp. 579-584, 2010.

[17] M. L. P. Tan, G. Lentaris, and G. A. Amaratunga, "Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET," Nanoscale Research Letters, vol. 7, article 467, 2012.

[18] Z. Johari, F. K. A. Hamid, M. L. P. Tan, M. T. Ahmadi, F. K. C. Harun, and R. Ismail, "Graphene nanoribbon field effect transistor logic gates performance projection," Journal of Computational and Theoretical Nanoscience, vol. 10, pp. 1164-1170, 2013.

[19] N. Bahador, M. L. P. Tan, M. T. Ahmadi, andR. Ismail, "Aunified drain-current model of silicon nanowire field-effect transistor (SiNWFET) for performance metric evaluation," Science of Advanced Materials, vol. 6, pp. 354-360, 2014.

[20] B. J. Sheu, D. L. Scharfetter, P.-K. Ko, and M.-C. Jeng, "BSIM: Berkeley short-channel IGFET model for MOS transistors," IEEE Journal of Solid-State Circuits, vol. 22, no. 4, pp. 558-566, 1987.

[21] X.Xuemei, D. Mohan, M. H. Tanvir, L.D.Darsen, M. Yang, and H. Jin, BSIM4 Homepage, 2013, http://www-device.eecs.berkeley. edu/bsim/?page=BSIM4 LR.

[22] H. Li, W.-Y. Yin, K. Banerjee, and J.-F. Mao, "Circuit modeling and performance analysis of multi-walled carbon nanotube interconnects," IEEE Transactions on Electron Devices, vol. 55, no. 6, pp. 1328-1337, 2008.

[23] S. Datta, Quantum Transport: Atom to Transistor, Cambridge University Press, 2005.

[24] M. L. P. Tan, Device and circuit-levelmodels for carbon nanotube and graphene nanoribbon transistors [Ph.D. thesis], Department of Engineering, University of Cambridge, Cambridge, UK, 2011.

[25] T. J. Kazmierski, D. Zhou, and B. M. Al-Hashimi, "A fast, numerical circuit-level model of carbon nanotube transistor," in Proceedings of the IEEE International Symposium on Nanoscale Architectures (NANOARCH'07), pp. 33-37, New York, NY, USA, October 2007.

[26] A. Balijepalli, S. Sinha, and Y. Cao, "Compact modeling of carbon nanotube transistor for early stage process-design exploration," in Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED '07), pp. 2-7, Portland, Ore, USA, August 2007.

[27] A. Rahman, J. Guo, S. Datta, and M. S. Lundstrom, "Theory of ballistic nanotransistors," IEEE Transactions on Electron Devices, vol. 50, no. 9, pp. 1853-1864, 2003.

[28] T. H. Ng, B. H. Koh, W. K. Chim et al., "Zirconium dioxide as a gate dielectric in metal-insulator-silicon structures and current transportmechanisms," in Proceedings of the IEEE International Conference on Semiconductor Electronics (ICSE '02), pp. 130-134, 2002.

[29] J. Xu, H. Li, W.-Y. Yin, J. Mao, and L.-W. Li, "Capacitance extraction of three-dimensional interconnects using element-by-element finite element method (EBE-FEM) and preconditioned conjugate gradient (PCG) technique," IEICE Transactions on Electronics, vol. E90-C, no. 1, pp. 179-187, 2007.

[30] "Process Integration, Devices, & Structures Process Integration," in International Technology Roadmap for Semiconductors (ITRS), 2005, pdf.

[31] M. Vujkovic, D. Wadkins, and C. Sechen, "Efficient post-layout power-delay curve generation," in Integrated Circuit and System Design. Power and Timing ModelIng, Optimization and Simulation, V. Paliouras, J. Vounckx, and D. Verkest, Eds., vol. 3728, pp. 393-403, Springer, Berlin, Germany, 2005.

[32] J. Guo, S. Hasan, A. Javey, G. Bosman, and M. Lundstrom, "Assessment of high-frequency performance potential of carbon nanotube transistors," IEEE Transactions on Nanotechnology, vol. 4, no. 6, pp. 715-721, 2005.

[33] Y. Yoon, Y. Ouyang, and J. Guo, "Effect of phonon scattering on intrinsic delay and cutoff frequency of carbon nanotube FETs," IEEE Transactions on Electron Devices, vol. 53, no. 10, pp. 2467-2470, 2006.

[34] Y. Wu, K. A. Jenkins, A. Valdes-Garcia et al., "State-of-the-art graphene high-frequency electronics," Nano Letters, vol. 12, pp. 3062-3067, 2012.

[35] V. K. Arora and A. Bhattacharyya, "Cohesive band structure of carbon nanotubes for applications in quantum transport," Nanoscale, vol. 5, pp. 10927-10935, 2013.

[36] V. K. Arora and A. Bhattacharyya, "Equilibrium and nonequilibrium carrier statistics in carbon nano-allotropes," in Physics of Semiconductor Devices, V. K. Jain and A. Verma, Eds., pp. 511-516, Springer, 2014.

[37] D. R. Greenberg and J. A. del Alamo, "Velocity saturation in the extrinsic device: a fundamental limit in HFET's," IEEE Transactions on Electron Devices, vol. 41, no. 8, pp. 1334-1339, 1994.

[38] M. L. P. Tan, T. Saxena, and V. K. Arora, "Resistance blow-up effect in micro-circuit engineering," Solid-State Electronics, vol. 54, no. 12, pp. 1617-1624, 2010.

[39] M. L. P. Tan, I. Saad, R. Ismail, and V. K. Arora, "Enhancement of nano-RC switching delay due to the resistance blow-up in InGaAs," Nano, vol. 2, pp. 233-237, 2007.

Huei Chaeng Chin, (1) Cheng Siong Lim, (1) Weng Soon Wong, (1) Kumeresan A. Danapalasingam, (1) Vijay K. Arora, (1,2) and Michael Loong Peng Tan (1)

(1) Faculty of Electrical Engineering, Universiti Teknologi Malaysia (UTM), 81310 Skudai, Johor, Malaysia

(2) Division of Engineering and Physics, Wilkes University, Wilkes-Barre, PA 18766, USA

Correspondence should be addressed to Michael Loong Peng Tan;

Received 10 December 2013; Revised 11 February 2014; Accepted 12 February 2014; Published 26 March 2014

Academic Editor: Tianxi Liu

TABLE 1: Design specifications C and S for various channel lengths.

Channel length (nm)   C (nm)   S (nm)   W (nm)

16                      30       8        46
32                      50       16       82
45                      60       20      100
65                      90       40      170
90                     120       50      220
180                    220      100      420

TABLE 2: Values for the coefficients A to G.

Coefficient           Value

A             -3.5000 x [10.sup.-2]
B             1.0737 x [10.sup.-3]
C             -2.7542 x [10.sup.-3]
D             2.3754 x [10.sup.-3]
E             -6.3691 x [10.sup.-4]
F             -8.8009 x [10.sup.-1]
G             -3.5738 x [10.sup.-4]

TABLE 3: Device parameters and performance metrics of GNRFET,
n-type, and p-type MOSFET.

Parameter                       GNRFET           n-type MOSFET

Electrical gate                   2.0                 1.0
oxide thickness

Gate dielectric                   25                  25
constant relative
to vacuum

Subthreshold swing              70.1704             61.7527

Drain-induced                   40.7448             35.2515
barrier lowering

On/off ratio,              3.42 x [10.sup.4]   1.25 x [10.sup.6]

Parameter                     p-type MOSFET

Electrical gate                    1.6
oxide thickness

Gate dielectric                    25
constant relative
to vacuum

Subthreshold swing               70.7253

Drain-induced                    36.6697
barrier lowering

On/off ratio,              6.9868 x [10.sup.5]

TABLE 4: ITRS 2005 based simulation parameters (adapted from [22]).

Technology process (nm)             32       22       14

Local and intermediate
  Width W (nm)                      32       22       14
  ILD thickness [t.sub.ox] (nm)   54.40    39.60    25.20
  [] (pF/m)               144.93   131.01   111.83
  [C.sub.gnrfet] (pF/m)           130.15   117.70   100.51
  Width W (nm)                      48       32       21
  ILD thickness [t.sub.ox] (nm)   110.40   76.80    52.50
  [] (pF/m)               179.78   163.30   139.30
  [C.sub.gnrfet] (pF/m)           163.81   148.90   126.78

TABLE 5: Interconnect capacitances for 16, 45, 65, and 90 nm nodes.

Capacitance                Technology process (nm)

                       90       65       45       16

[] (pF/m)    252.32   206.60   170.03   116.99
[C.sub.gnr] (pF/m)   226.87   185.70   152.76   105.01

TABLE 6: Load and output capacitance for logic gates NOT, two-input
NAND, two-input NOR, three-input NAND, and three-input NOR.

Gate logic         Capacitance

NOT                [C.sub.L] = [C.sub.gd1] + [C.sub.gd2] +
                   [C.sub.db1] + [C.sub.db2] + [C.sub.L]

Two-input NAND     [C.sub.1] = [C.sub.db1] + [C.sub.sb2] +
                   [C.sub.gd1] + [C.sub.gs2]

Two-input NOR      [[C.sub..sub.L] = [C.sub.db2] + [C.sub.db3] +
                   [C.sub.db4] + [C.sub.gd2] + [C.sub.gd3] +
                   [C.sub.gd4] + [C.sub.L]

Three-input NAND   [C.sub.1 = [C.sub.db1] + [C.sub.sb2] +
                   [C.sub.gd1] + [C.sub.gs2]

Three-input NOR    [C.sub.2 = [C.sub.db2] + [C.sub.sb3] +
                   [C.sub.gd2] + [C.sub.gs3]

                   [C.sub.L] = [C.sub.db3] + [C.sub.db4] +
                   [C.sub.db5] + [C.sub.db6] + [C.sub.gd3] +
                   [C.sub.gd4] + [C.sub.gd5] + [C.sub.gd6] +

TABLE 7: Propagation delay and average power consumption of GNRFET
and MOSFET with L = 16 nm and 1 [micro]m interconnect for various
logic gates.

Logic gates           Propagation     Average power,
                         delay,         [P.sub.av]
                     [t.sub.p] (ps)       (nJ/s)

                   GNRFET   MOSFET   GNRFET   MOSFET

Inverter           4.825    14.02     2.90    96.11
Two-input NAND     7.059    44.90     3.13    124.04
Three-input NAND   9.555    58.82     3.24    270.18
Two-input NOR      7.059    44.95     3.07    122.12
Three-input NOR    9.589    58.19     3.24    286.58
COPYRIGHT 2014 Hindawi Limited
No portion of this article can be reproduced without the express written permission from the copyright holder.
Copyright 2014 Gale, Cengage Learning. All rights reserved.

Article Details
Printer friendly Cite/link Email Feedback
Title Annotation:Research Article
Author:Chin, Huei Chaeng; Lim, Cheng Siong; Wong, Weng Soon; Danapalasingam, Kumeresan A.; Arora, Vijay K.;
Publication:Journal of Nanomaterials
Date:Jan 1, 2014
Previous Article:The fabrication and properties characterization of wood-based flame retardant composites.
Next Article:Graphene: one material, many possibilities--application difficulties in biological systems.

Terms of use | Privacy policy | Copyright © 2022 Farlex, Inc. | Feedback | For webmasters |