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Encapsulants for Board-Level Assembly -- New encapsulants are being developed that provide faster cure rates tosupport lower manufacturing costs.

Encapsulants are used in all types of electronic devices to support the reliability and performance of packaging technologies on the printed wiring board (PWB), including chip on board (COB), multicomponent subassemblies, flip chip on board (FCOB) and chip-scale packaging (CSP). Packaging technology selection depends on the reliability and performance expectations of the device. The most common decision criteria include reducing device size/miniaturization, improving device performance, simplifying the manufacturing process, maintaining flexibility for future changes to the device, and enabling in-house packaging of proprietary components.

Encapsulants that support board-level packaging vary greatly and will continue to change into the future. Early materials were formulated to provide a low coefficient of thermal expansion (CTE), a high elastic modulus and a high glass transition temperature (Tg) to hold the packages together during subsequent processing and reliability testing.

In the past 10 years, the need to mix encapsulants prior to use has been eliminated in favor of premixed liquid materials that are kept frozen until needed. More recently, tremendous strides have been made to improve adhesion to various packaging materials. Ease of encapsulant processing has improved dramatically as more is learned about surface tension/wettability and the effects of encapsulant manufacturing processes on flow characteristics. Flexible encapsulants with higher CTEs are demonstrating that materials that reduce package stresses often extend package life.

Glob Top Encapsulants for COB

Chip on board is a relatively old die packaging technique in which a bare die is affixed to the board, active side up, using a die attach adhesive (Figure 1). The die is then wire bonded to pads on the board. If left without coverage, the die and wire bonds would be subject to mechanical damage, contamination, leakage and shorting. Encapsulants completely cover the wires and are used to protect the die and maintain an electrically insulating layer between the wire bonds. Once glob top encapsulation is complete, the encapsulant will be the only visible element of the package.

Commercial-grade glob top encapsulants are generally filled epoxies with a low CTE (below 30 ppm/ degrees C) and a high modulus (greater than 2 GPa). Silica filler particles are commonly added to complex epoxy formulations to give the desired mechanical properties. Fillers and other additions provide the encapsulant resin with the high viscosity needed to cover the package and eliminate excess flow across the board. Good adhesion of the encapsulant to the die passivation, board surfaces and wires holds the package together, enabling it to withstand the stresses of thermal cycling and other challenges.

Adhesion is an important factor contributing to package reliability. Delamination at any interface within the package will eventually break one or more wire bonds, causing failure of the product. Thin layers of organic contamination are the most notorious causes of delamination. Preparation of the package prior to encapsulation is commonly used to enhance adhesion. Preparation can include ultraviolet-ozone/plasma treatment or liquid cleaning with organic solvents or detergents. Proper drying of the assembly prior to encapsulation also helps to ensure the most adherent interfaces.

Glob top encapsulants are generally dispensed onto the die and wire bonds through a needle-like dispense tip. The tip is moved to provide complete coverage with a minimum of material. The filler and other additives give the liquid the consistency of thick syrup, allowing enough flow to encapsulate between the wires without trapping air while preventing excess flow of the unconstrained material across the board surface. The high viscosity also gives the package a characteristic domed shape. This dome sometimes makes height control an issue with glob top encapsulants.

Most encapsulants are cured in a convection oven. Cure times can vary from minutes to hours. An initial cure at low temperature to form a solid gel may be needed to reduce shrinking of the material if board warpage is a concern. The encapsulant must then undergo a final cure at higher temperature.

Self-Leveling Encapsulants for Multicomponent Assemblies

These liquids are very similar to glob top encapsulants in almost all respects except that their lower viscosities enable them to flow to form a level seal over whatever they are covering (Figure 2). A confining wall or dam is required to contain the material within the desired area. Where cost or other concerns preclude use of a mechanical dam, a specialized class of very high viscosity liquid damming materials may be used. Dams are often made of a similar or identical chemistry as the matching encapsulant, but they are formulated with sufficient filler and other additives to create a thick, paste-like consistency.

Traditional self-leveling encapsulants offer similar mechanical and adhesive properties to glob tops, but feature improved flow between fine-pitch wire bonds, superior finished package appearance and enhanced height control. These advantages make self-leveling encapsulants popular for high-volume "dam and fill" encapsulation of integrated circuit (IC) packages. Their appearance and height control advantages also make them a favorite in board-level applications in which a large area must be sealed or covered. Self-leveling encapsulants provide an easy way to encapsulate a number of wire-bonded die or to provide mechanical, environmental or tamper protection to a grouping of mixed component types.

As with other encapsulants, cleaning is usually recommended prior to dispensing to ensure the best possible adhesion, especially if bare die or wire bonds are to be covered and protected. If a dam is not already in place, one may be dispensed as a bead from a needle-tipped pump. The encapsulant is then dispensed, typically in a spiral pattern, until the desired height is reached. Overfilling may cause the encapsulant to spill over the dam or may push an ungelled, dispensed dam out of place. Curing processes from minutes to hours are available for self-leveling encapsulants. To ensure a level encapsulant surface, the cure oven itself must also be level.

A common consequence of attaching large expanses of encapsulant and PWB, warpage is probably the most serious single issue faced when encapsulating large areas. To minimize warpage, low CTE encapsulants have been developed to reduce cumulative thermal expansion mismatch. In cases where a low CTE, high modulus encapsulant is not essential, applications of unfilled, low Tg materials have shown that warpage on large assemblies can be practically eliminated.

Underfill Encapsulants for FCOB

Flip chip on board (FCOB) is an advanced die packaging style that has become fairly common on devices where superior electrical performance or reduced size is critical (Figure 3). The die is mounted on the board with the active side down, opposite of the COB orientation. Instead of wire bonds, electrical connection between the board and die consists of short (typically 100 mm or less) electrically conductive bridges, also called joints or interconnects, that connect each die pad to a corresponding board pad directly below. The interconnects are commonly metallic, but may also be a metal-filled organic material.

Spacing between interconnects is characteristically small (less than 0.4 mm) relative to those found in CSPs and other surface-mount components. Attachment of the die to the board on a conventional surface-mount assembly line is most commonly performed at the front end of the line where other packages and devices are attached. Left unprotected, a flip chip's electrical interconnections are subject to damage from moisture, corrosion, mechanical impact and other factors. Any CTE mismatch between the silicon die and the board acts to fatigue the tiny interconnects during temperature excursions.

Underfill encapsulants protect interconnects, hold the package together and evenly distribute stresses caused by CTE mismatch between the board and die. While underfills normally extend interconnect life by 100 to 1,000 times, the usual failure mode for FCOB is delamination of the die from the underfill passivation.

Similar to other encapsulants, low CTE (less than 30 ppm/ degrees C), high modulus (greater than 5 GPa), and high Tg (above 140 degrees C) were traditional trademarks of a "good" FCOB underfill. Because delamination and warpage-not interconnect fatigue-are the major issues inhibiting qualification of new packages, device manufacturers are now interested in materials that exhibit higher adhesion and those able to produce packages with lower warpage. Lower modulus materials with higher CTEs (greater than 40 ppm/ degrees C) and lower Tgs (even below 100 degrees C) are now commonly available. New additives and chemistries have improved adhesion, even in the presence of moisture and extreme heat.

Underfills are typically deposited using a needle-tipped dispensing pump. The material is dispensed as a bead along the edges of the die, allowing the underfill to pull under the die by capillary forces. Control of the dispense pattern is a critical factor in ensuring that the whole gap between the die and board is filled with encapsulant. Dispensing underfill too quickly (mass per second) causes excess encapsulant to spread onto the board around the die, which can affect other components located close by. Underfill surrounding and wetting the die edges beyond the footprint of the chip is called a fillet. A small keep-out zone devoid of other components is required around the die to accommodate the underfill fillet.

The conventional "capillary flow" underfill process imposes some rather unique requirements on FCOB encapsulation. Any debris or organic residues in the gap under the die must be wettable, soluble in the underfill or removed beforehand to ensure uniform flow of the encapsulant and good adhesion after cure. Lack of good wetting is responsible for many cases of air entrapment during capillary flow. In comparison with other encapsulants, FCOB underfills must be very low viscosity materials so as not to impede flow under the die.

Some type of thermal cure is always required to develop the Tg and modulus properties of the material. Most FCOB underfills now fully cure in five minutes or less at 165 degrees C or lower, which enables cure in a tunnel cure oven or converted solder reflow oven. Longer cures or higher throughputs require multiple-lane tunnel ovens or vertical inline ovens.

FCOB encapsulants should be dispensed onto a dry board to prevent moisture problems that can impact adhesion. Any moisture evolving from the board can form voids in the gap between the chip and the die, displacing underfill and exposing interconnects to corrosion, fatigue and creep. Temperature excursions above the interconnect melting point can actually destroy the joints as interconnect material is forced into the voids. In many cases, solder reflow processes at the front end of the line can sufficiently dry the assembly, but boards exposed to more than a few hours of ambient moisture require drying. Because each assembly line and assembly are unique, the need for baking varies from application to application.

Several new advanced underfill materials promise space, labor or capital cost savings over capillary flow materials. Removable underfill materials are now available that enable the removal and replacement of a flip chip after the underfill is cured. These materials soften or degrade, usually under heat exposure, permitting removal of the die. Underfill and interconnect residues can then be removed and a new chip attached and underfilled as before. Removable underfills offer benefits when known good die are not available or are too expensive, or when manufacturing yields are poor.

New fluxing or no-flow underfills may save money by eliminating the need for a dedicated cure oven (Figure 4). These materials are generally designed to support the use of solders as the electrical interconnection. Underfill is dispensed prior to die placement, then the die is placed directly into the encapsulant. Next, the board undergoes reflow, during which the material cures. A fluxing function built into the material ensures thorough reflow of the joints.

No-flow underfills eliminate large fillets and flux residue-induced adhesion issues. Boards should be dry prior to dispensing to preclude voiding during cure. Because no-flow underfills are unfilled, their moduli are lower (less than 3 GPa) and their CTEs quite high (greater than 50 ppm/ degrees C) relative to filled materials, which may make them unreliable with exceptionally large (greater than 7 mm) FCOB die.

Now under development for FCOB are wafer-scale underfills that are applied prior to wafer dicing. These may eliminate in-line dispensing and make FCOB processing as simple as placing the die and reflowing, just as for conventional surface-mount component attach.

Underfill Encapsulants for CSP

Chip scale packages are small IC packages typically employing an array of solder balls (0.5 mm pitch or greater) underneath the package to make electrical connection to the board. In many ways, CSPs both resemble and behave like FCOBs, but larger solder balls make package placement easier and reliability superior. CSPs present a favorable alternative to FCOB in many cases where smaller component size is desired, but smaller FCOB components are unavailable or the FCOB process is too expensive.

While reliable in most board-level life testing, many CSPs and the boards that support them fail when exposed to impact forces or when dropped. Failure is often due to cracking of the joints or disconnection of the board attachment pads. Underfill encapsulants can eliminate these problems by reducing board flexure and spreading impact stresses over the area of the package rather than the area of the attachment joints.

Conventional FCOB underfills were the first used for reinforcing CSPs, although they are over-designed for the light-duty performance expected of them. While processed similarly to capillary FCOB underfills, such issues as board moisture and flux compatibility are not nearly as important. Removable and no-flow underfills are also candidates for CSPs. Lower cost materials that are optimized as CSP underfills are now emerging as well. Unfilled, low Tg underfills appear viable for impact reinforcement. These materials combine low cost, easy processing and removability with rubber-like shock absorbing properties.


Board-level packaging is becoming increasingly complex and specialized. This trend is reflected in the variety and sophistication of the encapsulants needed to ensure device reliability. New encapsulants continue to be developed that are easier to use, with faster cures to support lower manufacturing costs. Greater reliability requirements are accelerating the conversion of package-level encapsulant technology for board-level assembly.

New packaging technology will require lower volumes of higher-tech encapsulants. Techniques for making, testing and dispensing encapsulants will demand greater understanding of complex raw material interactions, interface chemistry, adhesion and pump technology.

Photonics packaging is probably the greatest challenge facing encapsulant manufacturers and users, and new high-volume processes are yet to be established. Emergence of a large variety of new processing techniques and mechanical properties can be expected. Suppliers who quickly adapt to the needs of this rapidly developing industry will see their chemistries and properties establish the benchmark for the industry's expectations.


George Carson is a research associate with Dexter Electronic Materials, Industry, CA; e-mail:

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Author:Carson, George
Publication:Circuits Assembly
Geographic Code:1USA
Date:Apr 1, 2001
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