Embedded Passives: Promising Improved Performance -- System costs must be weighed against performance improvements when considering the use of embedded passives.
Designers have several choices for accomplishing the passive functions: discrete passives, array passives, passive networks, integrated passive devices and embedded passives. Table 2 describes these passive components in detail. In addition to these components, designers may also select on-chip passives, where the passive elements are fabricated along with the active elements as part of the semiconductor wafer. This article will focus on embedded passives, highlighting their advantages, challenges and cost considerations and the technology developments required to make this approach widely adopted by industry.
What is an Embedded Passive?
Embedded passives are buried (embedded or integrated) into the substrate material. The substrate might be a small piece of ceramic, a large FR-4 board or a small laminate package substrate. As long as the passive elements are an integral part of the substrate, they are called embedded or integral passives; but not to be confused with integrated passive devices (IPDs). The deciding characteristic is that the passive component does not need to be mounted on or connected to the substrate. It is distinguished from the "super component" (IPD) because it acts as the system board. Although capacitors, resistors and inductors are all candidates for embedding, the greatest interest is currently focused on capacitors and resistors.
Both capacitors and resistors can be embedded as individual, "singulated" components when a particular value is needed. Alternatively, if the capacitance only has to be greater than a minimum value, the capacitance can be distributed as an entire plane of capacitance between the power and ground planes in the PCB. With this configuration, the distributed capacitance can be accessed by dropping a single via (low inductance) down to the power plane. This method of accessing capacitance has a distinct advantage for decoupling capacitors where the performance is limited by the total inductance of the connections and the component.
Examples of singulated and distributed planar construction are shown in Figures 1 and 2. In singulated construction (Figure 1), the resistor (R1) becomes embedded on the resistor plane, numerous resistors may be embedded, depending on the design. The resistor layer covers the entire surface and is etched away to provide the resistors desired. Similarly, the capacitors (C1 and C2) become electrode patterns on a dielectric layer that is buried in the substrate.
In distributed planar construction (Figure 2), the single decoupling capacitor covers the entire plane. Each decoupling requirement drops down to the same power-ground electrode plane.
The components used for embedded passives can be made from prefabricated laminate material. Resistors can also be made by plating the resistive layer in additive fashion on the resistor site. With resistors, a resistive coating is placed over the entire sheet of laminate and then processed. For capacitors, the epoxy is replaced with a thin low-dielectric material. Other ways of forming embedded devices include stenciling materials and plating.
The primary goal of embedding passives in the substrate has been to reduce the amount of surface area required for passive devices. However, by being located directly beneath the integrated circuit (IC) it services, an embedded passive has shorter leads and lower inductance, both of which result in improved electrical performance. Embedded passives have no solder joints, resulting in greater reliability and reduced amounts of lead.
Despite the potential advantages of embedded passives, they have not gained the wide acceptance predicted by the National Electronics Manufacturing Initiative's (NEMI, Herndon, VA) 1998 roadmap. Some of the reasons are lack of flexibility when design changes are needed, lack of available design software, and the accelerated use of the tiny 0201 devices, even though they are difficult to handle.
Although the handheld market might be expected to drive the use of embedded passives for reduced surface area, the latest NEMI roadmap found that embedded passives are being driven more by the high performance sector, because of their improved electrical characteristics and electromagnetic interference (EMI) suppression.1
For most applications, the integral resistor seems to be simply a one-for-one substitution, but not so for capacitors. Signal integrity issues, as well as EMI suppression, seem likely to be handled with planar distributed capacitance replacing multiple discretes. In fact, the EMI improvements might turn out to be the most important factor driving the implementation of embedded passive components.
In cellular phones, the number of 0201 size passives used instead of embedded passives on the main boards is increasing. Also, the use of "super components" or modules, which usually contain embedded passives, is increasing.
To address the economic viability of embedded passives, the impacts of the following competing effects must be considered:
- possible decreased board areas due to a reduced number of discrete passive components
- decreased top surface wiring density requirements due to the integration of resistors and bypass capacitors into the board
- increased wiring density requirements due to decreased board sizes
- increased number of boards fabricated on a panel due to decreased board size
- increased board costs per unit area
- decreased board yields
- decreased board fabrication throughputs
- decreased assembly costs
- increased overall assembly yields
- decreased assembly-level rework.
The opposing nature of many of these effects complicates the task of determining the overall economic impact of replacing discrete passives with embedded passives. In general, such analysis yields application-specific guidelines instead of general rules of thumb. In fact, the very nature of trade-off analysis is that the greater the detail necessary to accurately model a system, the less general and more application-specific the result.
To gain insight into the economics of embedded passives, the NEMI roadmap performed an application-specific economic analysis of the conversion of discrete passive components (resistors and capacitors) to integral passives embedded within a PCB. The model performed three basic analyses:
- Board size analysis was used to determine new board sizes, new layer counts and the number of boards that can be fabricated on a panel.
- Panel fabrication cost modeling, including a cost of ownership model, was done to determine the impact of throughput reductions associated with fabricating integral passive panels.
- Assembly modeling determined the cost of assembling all discrete components plus the associated inspection and rework.
The combination of these three analyses was used to evaluate size/cost tradeoffs for several example systems. The system attributes that drive cost effectiveness of integral passives were determined for each case.
In all cases, the analyses found integral (embedded) resistors to be generally cost effective, with the most significant economic impact coming from either number-up increases resulting from board size reductions or layer count decreases due to reductions in routing requirements. The analyses considered integral resistors fabricated directly on wiring layers, as opposed to dedicated integral resistor layers assumed in previous studies.2,3 Therefore, the results cannot be generalized or expressed in terms of component costs per unit area.
The cost of adding integral resistors is driven by board fabrication profit margin, which is a fractional increase in board cost and much smaller in absolute terms for high number-up. Cost reduction is through displacement of discrete parts. As expected, if a technology that adds resistors directly to the wiring layers is used, integral resistors can become economically viable when considerably fewer are integrated than for layer addition technologies.
For the applications considered, integral (embedded) capacitors become economical when the capacitor density reaches 0.7 to 1.1 discrete capacitors per cm2 (4.4 to 6.9 capacitors per in.2) or greater. This density is smaller than the 3 components per cm2 previously proposed.4 This result is due to the material costs assumed (from the NEMI roadmap) that represent mature technology material costs.
The Future of Embedded Passives
That any product will use only one type of passive component is highly unlikely. The relative percentage of embedded passives, IPDs and discretes will be dictated by stability of the design, signal integrity at high speed and spectrum of component values.
Widespread implementation of embedded passives will require additional materials research and a cost-effective infrastructure for design, manufacture and test. Embedded passive resistors are planar resistive elements incorporated within the substrate by what is considered to be a mature technology. Significant progress has resulted in the development of several new materials options that enable more functionality and flexibility in the application of integral substrates. Some critical areas for further development are: high yielding processes; microvia technology; higher power densities; prototyping of integral substrates; design systems; and test and trim.
High yielding processes
Many new materials under consideration require processes that are new to circuit board fabricators; for example, screen printing. Some require processes that are not currently being done, such as laser trim on FR-4. Well-defined areas, thickness control and achieving tight tolerances are critical needs of the manufacturing process. Some progress has been made by the Advanced Embedded Passives Technology (AEPT) consortium,5 but additional progress is needed for materials to become cost and performance competitive.
High-density interconnect (HDI) substrates, including microvias, are an enabling technology for integral passive components and array packaging. High-speed design only becomes useful when embedded passives are used in conjunction with microvias to obtain the lowest possible inductance in the interconnect.
Higher power densities
The power density of the available materials is rated at 10 W/in.2 or more, which is adequate in the near term. However, as densities increase, this rating may become inadequate.
Prototyping of integral substrates
The turnaround time for a revision of resistor values and placement must be three days. This factor is closely tied to the ability to design with greater accuracy. This problem can be overcome by only targeting, for example, 40 percent of the passive devices that are relatively stable and do not have any propensity to change.
Embedded passive designs are created manually using standard computer-aided design/computer-aided manufacturing (CAD/CAM) layout tools. These tools support component placement and autorouting but not component simulation or electrical modeling. The lack of automated design and modeling software is the biggest obstacle to the integration of capacitor and some resistor applications in frequency-sensitive designs.
Test and trim
Standard data formats such as custom software, scripts and netlists used for inner layer and bare board electrical testing do not provide sufficient information to identify and test buried components. The first test and trim equipment for embedded resistors debuted at this year's IPC Expo, April 1-5, Anaheim, CA.
Shift of Responsibility
Embedded passive technology will cause a major shift in responsibilities from the custom manufacturer/assembler to the PCB fabricators. The PCB fabricator will now be responsible for delivering a board with correct passive values as well as electrical performance. The fabricators will have to develop new processes for the construction or embedding technologies required for the new passives.
The new processes and technologies will result in lower yields, especially in the start-up and transition phase. This reduction will be based on both the fabricators' new process controls and on the defect density or variability of the new passive materials. Fabricators will have to set up systems to screen incoming passive materials and develop test coupons for measuring and tracking lot performance and results.
Rework will be affected. PCB fabricators will need to develop rework procedures at the layer level. These procedures will be critical to throughput and, therefore, the final cost of the technology.
Inventory is an issue. Many of these materials are quite costly and can only be used for specific embedded applications. This factor will increase inventory cost and the possibility of costly scrap for outdated materials.
Perhaps one of the most critical areas of concern is test. An increase may occur in the cost of testing finished boards, especially if several decades of values are on the board. Additional testing will be required to electrically test the inner layers or cores prior to lamination. Fabricators will have to understand the impact of their processes on material changes such as drift and temperature coefficient of resistance. The correlation between layer testing and final board performance will have to be understood and correlated with customers' assembly tests.
Standardization is needed to move embedded devices into the mainstream. IPC is drafting specifications for a materials performance standard (IPC-4902) for embedded passives. Underwriters' Laboratories has also initiated a program to review the performance of new materials.
The bottom line is that the fabricator, assembler and end user must all understand and carefully weigh system costs against performance improvements when deciding whether to use embedded passives in their product designs. Initially, the use of embedded passives will be driven by the need for better high-performance package characteristics, both signal integrity and EMI suppression. Reduced board size is a secondary driver because 0201 devices can serve that purpose in handheld applications until about 2005. However, embedded passives will require many new materials and tools as well as a shift in responsibility between the board supplier and the end user.
1. NEMI. 2000 Roadmap. Herndon, VA: National Electronics Manufacturing Initiative.
2. Ohmega Technologies Inc. Ohmega-Ply Cost Analysis. White paper. Culver City, CA, www.ohmega.com.
3. Takken, T., and D. Tuckerman. 1993. Integral decoupling capacitance reduces multichip module ground bounce. Proc. IEEE Multi-chip Module Conference. Santa Cruz, CA, pp. 79-84.
4. Realff, M., and C. Power. 1998. Technical cost modeling for decisions in integrated vs. surface mount passives. Proc. IMAPS 3rd Advanced Technology Workshop on Integrated Passives Technology. Denver, CO, April.
5. AEPT. The Advanced Embedded Passives Technology project is being conducted by the National Center for Manufacturing Sciences; http:// aept.ncms.org/ and http://www.ncms.org/.
Larry Marcanti is senior manager, advanced design technology, with Nortel Networks, Richardson, TX; e-mail: email@example.com. Joseph P. Dougherty, Ph.D., is associate professor of materials and electrical engineering with The Pennsylvania State University, University Park, PA; e-mail: firstname.lastname@example.org.
Microvias today are used in threshold and state-of-the-art products, such as high-end laptop computers, video recorders, high-end cell phones and in special niche markets. These products are being produced with >75 mm lines and spaces.
Microvia board cost is driven by density. Currently, the total cost for a high-density board with microvias is roughly the same as the total cost for an equivalent density FR-4 board. High-density board costs, both printed board and microcircuit boards, will decrease as more technologies mature and additional fabricators begin to manufacture these technologies in volume.
Over the last two years, the technologies used for microvia formation in build-up constructions have matured significantly, with a commensurate growth in infrastructure development. Laser via formation has overtaken photovia technology both in product volume and number of manufacturing sites. This trend does not imply a reduction in the volume of photovia product but, rather, that fabricators newly adopting build-up processes have found laser drilling more cost effective or versatile. Reportedly, the ease of adoption of laser processes, lower initial capital requirements and improved overall yields are factors.
The remarkable productivity improvements in laser drilling also cannot be ignored, with 2x throughput improvements introduced almost annually. Fortunately, the necessary laser systems and dielectric materials are readily available from North American manufacturers.
An important development is the hybrid laser that contains an ultraviolet yttrium aluminum garnet (YAG) laser for copper cutting and a carbon dioxide laser for high productivity dielectric removal. Two North American companies now offer this technology, and several other companies are promising systems. Hybrid laser systems have been shown to drill over 250 holes per second through 12-micron foil and 50-micron organic dielectric. Dielectric resins with organic reinforcements, such as aramids or expanded PTFE, can be laser drilled at more than three times the speed of glass fiber-reinforced resins. The higher productivity of these reinforcements is causing fabricators to look beyond traditional inorganic glass reinforcements.
Resin-coated foil has also become a major candidate for laser drilling applications. However, it does not have the benefits of low coefficient of thermal expansion (CTE) and degree of dimensional stability offered by nonwoven aramid reinforcement, nor does it have the low dielectric constant or the low loss offered by expanded PTFE. In the absence of a compliant chip package, a low in-plane CTE contributes to reliable chip-to-PCB solder joint connections, and laminates with superior dimensional stability enable the formation of microvia interconnects to multiple layers without sequential build-up processes.
Photovia formation continues to grow in large volume applications, such as PCBs for portable PCs, where the simultaneous formation of a very large number of microvias offers favorable economics.
While microvia technology is growing in product usage in the electronics industry, volume manufacturing is largely confined to the Pacific Rim, primarily Japan. Although high-density interconnect (HDI) boards with microvias are available from several North American suppliers, more than 90 percent of the production volumes still come from the Far East. As microvia technology continues to improve in terms of performance and cost metrics, it will find its way into broader product applications. As this trend occurs, regional supply chains without microvia volume capability could see shrinking PCB market.
-Ronald W. Gedney, NEMI, Herndon, VA, email@example.com://www.circuitsassembly.com
Copyright [copyright] 2001 CMP Media LLC
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|Author:||Dougherty, Joseph P.|
|Date:||Jul 1, 2001|
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