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Electronically Tunable Quadrature Sinusoidal Oscillator with Equal Output Amplitudes during Frequency Tuning Process.

1. Introduction

Quadrature sinusoidal oscillators are very important circuits in numerous applications such as communication, sound system, instrumentation, control system. Especially in modulation system, the quadrature oscillator is used to generate the carrier signal for quadrature amplitude modulation (QAM) and single-sideband modulation (SSB) [1,2]. Most of sinusoidal oscillator designs required the following features: low THD of the quadrature sinusoidal output, independent control of frequency of oscillation (FO) and condition of oscillation (CO) [3], using minimum number of active and passive element [4], electronic controllability [5] and so on. However, the amplitude of quadrature sinusoidal output should be considered too. To avoid the use of external amplifier, the expected amplitude of quadrature output should be equal for all frequency or during tuning FO.

The design of electronic circuit in analog signal processing has been emphasized in the use of active building block [6-8]. Particularly, the electronically tunable active building blocks have attracted significant research attention since analog circuits using electronically tunable active building block give more fine-tuning than adjusting the value of passive device. The voltage differencing current conveyor (VDCC) [9,10] is a recently reported versatile active building block used in the realization of analog signal processing circuits. VDCC is also attractive due to its capability of electronic controllability. The analog circuits using VDCC as active element have been found in the literature, for examples, universal filter [11-14], first-order all-pass filter [15], ladder filter [16], passive element simulator [10,17-21], and square and triangular wave generator [22]. The VDCC-based sinusoidal oscillators have been proposed in [19,23-26]. In [19], the Colpitts oscillator using VDCC-based capacitance multiplier was proposed. In this oscillator, the FO and CO can be independently tuned. It can provide quadrature output waveform but the amplitude of quadrature output voltage is not equal during tuning the frequency. Also it requires dual output terminal VDCC ([W.sub.n] and [W.sub.p] terminal). The simple current-mode oscillator using single VDCC and grounded passive elements was presented in [23]. The FO and CO can be orthogonally controlled. The current-mode quadrature sinusoidal waveform is obtained. However, the FO cannot be electronically tuned without affecting CO. Also the amplitude of quadrature output waveform is not equal during tuning the frequency. The simple voltage-mode quadrature oscillator using single VDCC, two grounded resistors, and two grounded capacitors was implemented in [24]. The FO and CO can be orthogonally controlled. The FO can be electronically tuned without affecting the CO. However, the amplitude of quadrature output waveform is not equal during tuning the frequency. In [25], the quadrature oscillator using two VDCC, two grounded resistors, and two grounded capacitors was presented. The FO and CO can be independently/electronically controlled. However, the amplitude of quadrature output waveform is not equal during tuning the frequency. In [26], the quadrature oscillator using single controlled gain VDCC (CG-VDCC) and two grounded capacitors was presented. The FO and CO can be independently/electronically controlled. However, the amplitude of quadrature output waveform is not equal during tuning the frequency. Also the internal construction of CG-VDCC using the commercially available ICs is quite complicated.

The idea behind this work is to present the quadrature sinusoidal oscillator emphasized on the use of VDCC as active element. The amplitude of quadrature output waveform is equal during tuning of frequency. Also, the frequency of oscillation can be electronically tuned without affecting the condition of oscillation.

2. Proposed Circuit and Operation

2.1. Voltage Differencing Current Conveyor (VDCC). In this design, the active building block (ABB) called voltage differencing current conveyor (VDCC) is used as main active device. The international construction of CMOS VDCC was proposed by Kacar et al. [10] in 2014. It is five-port device, namely, P, N, Z, X, and W port. The high impedance voltage input ports are P and N. The high impedance current output ports are Z and W port. The low impedance voltage output port is X port. In the original version of VDCC the output current at W port provides the output current both positive and negative direction called [W.sub.n] and [W.sub.p] ports. However, in this purpose, only single W port is required. This can reduce the current tracking error at W port and can reduce the number of transistor in VDCC. The electrical symbol and equivalent circuit of VDCC are shown in Figure 1. The ideal electrical properties of VDCC are shown in

[mathematical expression not reproducible], (1)

where [g.sub.m] is the transconductance gain. For CMOS VDCC, [g.sub.m] is controlled by DC bias current IB as follows:

[g.sub.m] = [square root of ([I.sub.B][[mu].sub.n][C.sub.ox](W/L))]. (2)

where [I.sub.B] is bias current, [[mu].sub.n] is mobility of the carrier for MOS transistors, [C.sub.ox] is gate-oxide capacitance per unit area, W is effective channel width, and L is effective channel length, respectively. The internal construction of CMOS VDCC is shown in Figure 2 [10]. The VDCC can be constructed from commercially available ICs as shown in Figure 3. It consists of LM13700 [27] and AD844 [28]. This construction contains only single w terminal. [g.sub.m] for this construction is given as

[g.sub.m] = [I.sub.B]/2[V.sub.T], (3)

where [V.sub.T] is the thermal voltage.

2.2. Proposed Oscillator. The proposed oscillator consists of two VDCCs, two resistors, and two grounded capacitors. The quadrature output voltages [V.sub.o1] and [V.sub.o2] are the voltage dropped at Z port of VDCC1 and VDCC2, respectively. However, the output voltages are taken from the non-low-impedance output nodes, so the voltage buffers are needed for cascading. The output current IQ with high impedance flows from W port of VDCC2. Taking into consideration the ideal port characteristics involved in VDCC as referred above (2) and the relevant notations appearing in Figure 4, the characteristic equation is as follows:

[s.sup.2] + s(1 - [R.sup.2]/[R.sub.1]) [g.sub.m1]/[C.sup.1] + [R.sub.2][g.sub.m1][g.sub.m2]/[R.sub.1][C.sub.1][C.sub.2] = 0. (4)

From (4), the frequency of oscillation is given as

[[omega].sub.0] = [square root of ([R.sub.2][g.sub.m1][g.sub.m2]/[R.sub.1][C.sub.1][C.sub.2])]. (5)

Subsequently, the condition of oscillation is given as

[R.sub.2] [greater than or equal to] [R.sub.1]. (6)

It is evident from (5) and (6) that the frequency of oscillation can be controlled by [g.sub.m1] and [g.sub.m2] without affecting the condition of oscillation. Moreover, the frequency of oscillation can be electronically tuned via [g.sub.m1] and [g.sub.m2]. If [R.sub.2] [congruent to] [R.sub.1], the frequency of oscillation is rewritten as

[[omega].sub.0] = [square root of ([g.sub.m1][g.sub.m2]/[C.sub.1][C.sub.2])]. (7)

From the circuit in Figure 4, the voltage ratio of [V.sub.o1] and [V.sub.o2] is as follows:

[V.sub.o2]/[V.sub.o1] = [g.sub.m2]/s[C.sub.2]. (8)

It is found from (8) that the output voltages [V.sub.o2] and [V.sub.o1] are 90-degree phase difference which is called quadrature signal. The phase of output voltage [V.sub.o1] leads the phase of output voltage [V.sub.o2] to 90 degrees. At frequency of oscillation ([[omega].sub.0]), the magnitude of output voltage ratio in (8) becomes

[absolute value of [V.sub.o2]/[V.sub.o1]] = [g.sub.m2]/[[omega].sub.0][C.sub.2]. (9)

Substituting (7) into (9), the magnitude of output voltage ratio in (9) becomes

[absolute value of [V.sub.o2]/[V.sub.o1]] = [square root of ([g.sub.m2][C.sub.1]/[g.sub.m1][C.sub.2])]. (10)

If [C.sub.1] = [C.sub.2] and [g.sub.m1] = [g.sub.m2], the magnitude of output voltage ratio is equal to unity. Therefore, the tune of frequency of oscillation with electronic method can simultaneously change [g.sub.m1] and [g.sub.m2] to keep the amplitude of output voltages [V.sub.o1] and [V.sub.o2] equal. This makes the sinusoidal output voltages meet low total harmonic distortions (THD). Moreover, if VDCC is constructed from commercially available ICs as illustrated in Figure 3 where its [g.sub.m] is linearly tuned by bias current, the frequency of oscillation can be linearly controlled.

3. Analysis of Frequency Stability

The analysis of frequency stability of the proposed circuit is done by using the definition of the frequency stability factor ([S.sub.F]) given in [29,30]

[S.sub.F] = [d[phi](u)/du|.sub.u=1], (11)

where u = [omega]/[[omega].sub.0] is normalized frequency and [phi](u) is the phase expression of the open loop transfer function of circuit in Figure 4 and its transfer function is expressed as follows:

[mathematical expression not reproducible]. (12)

With the above definition, the frequency stability factor of the proposed oscillator is given as

[S.sub.F] = 2[square root of (n)], (13)

where [C.sub.1] = [C.sub.2] = C, [R.sub.1] = [R.sub.2] = R, [g.sub.m1] = 1/R, and [g.sub.m2] = n/R.

4. Effect of Nonideal Current/Voltage Gains and Parasitic Elements

Practically, the influence of nonideal current/voltage gain and parasitic element in VDCC will affect the performances of the proposed oscillator. Considering the these gains, the electrical properties of VDCC are given as [I.sub.z] = [g.sub.m]([V.sub.P] - [V.sub.N]), [V.sub.x] = [beta][V.sub.z], and [I.sub.z] = [alpha][I.sub.x], where [beta] and [alpha] represent the voltage and current gain error, respectively. At high impedance ports [V.sub.P], [V.sub.N], Z, and W, a parallel parasitic combination of a resistance and a capacitance appears and they are denoted as [R.sub.P], [C.sub.P], [R.sub.N], [C.sub.N], [R.sub.Z], [C.sub.Z], [R.sub.W], and [C.sub.W], respectively. At low impedance port x, a series parasitic resistance appears and it is denoted as [R.sub.x]. These parasitic impedances affect the performance of the proposed oscillator. Taking them into account, the characteristic equation of the circuit in Figure 4 is obtained as

[mathematical expression not reproducible], (14)

where [Y.sub.1] = s([C.sub.1] [C.sub.N1] + [C.sub.Z1] + [C.sub.P2]) + [G.sub.N1] + [G.sub.Z1] + [G.sub.P2], [Y.sub.2] = s([C.sub.2] + [C.sub.z2]) + [G.sub.z2], [Y.sub.3] = s([C.sub.P1] + [C.sub.W1]) + [G.sub.P1] + [G.sub.W1], and [R*.sub.1] = [R.sub.1] + [R.sub.x1] + [R.sub.x2]. If the operational frequency [f.sub.op] [much less than] 1/[([C.sub.P1] + [C.sub.W1])([R.sub.P1] [parallel] [R.sub.W1])], the characteristic equation in (13) becomes

[mathematical expression not reproducible], (15)

where [C*.sub.1] = [C.sub.1] + [C.sub.N1] + [C.sub.Z1] + [C.sub.P2], [G*.sub.2] = [G.sub.N1] + [G.sub.Z1] + [G.sub.P2], and [C*.sub.2] = [C.sub.2] + [C.sub.z2]. From (14), the frequency of oscillation is obtained as

[mathematical expression not reproducible]. (16)

Subsequently, the condition of oscillation is given as

[mathematical expression not reproducible]. (17)

From the circuit in Figure 4, the nonideal voltage ratio of [V.sub.o1] and [V.sub.o2] is as follows:

[mathematical expression not reproducible]. (18)

Substituting (16) into (18), the magnitude of output voltage ratio in (18) becomes

[mathematical expression not reproducible]. (19)

It is found in (19) that although [C.sub.1] = [C.sub.2], [R.sub.1] = [R.sub.2], and [g.sub.m1] = [g.sub.m2], the magnitude of output voltage ratio is not equal to unity. According to (19), the phase response of [V.sub.o2] to [V.sub.o1] becomes

[mathematical expression not reproducible]. (20)

5. Experimental Results

In order to verify the performances of the proposed oscillator in Figure 4, the experiment was performed by using VDCC constructed from commercially available ICs, LM13700 from Texas Instruments Incorporated and AD844 from Analog Devices, Inc. as illustrated in Figure 3. The power supply voltages of experiment were [+ or -]5 V. The oscillator was designed to obtain the frequency of oscillation, [f.sub.0] = 50 kHz. From (7), an experimental setup was made by taking [C.sub.1] = [C.sub.2] = 10 nF, [R.sub.1] = 7.23 k[OMEGA], [R.sub.2] = 7.52 k[OMEGA], and [I.sub.B1] = [I.sub.B2] = 163 [micro]A. With the above component values, the experimented frequency of oscillation becomes [f.sub.0] = 47 kHz. The deviation of theoretical and experimental frequency of oscillation is about 6%. The deviation of theoretical and experimental value stems from the parasitic resistances and capacitances as shown in (16). However, [f.sub.0] = 50 kHz was obtained when [I.sub.B1] and [I.sub.B2] were set as 180 [micro]A. The measured sinusoidal quadrature waveforms [V.sub.o1], [V.sub.o2] and their frequency spectrums are illustrated in Figure 5. The output current waveform and its spectrum which is measured from the voltage dropped on load resistor 10 k[OMEGA] are depicted in Figure 6. To obtain the frequency of oscillation [f.sub.0] = 100 kHz, the bias currents [I.sub.B1] and [I.sub.B2] were set to 370 [micro]A. Figure 7 represents the output waveforms [V.sub.o1] and [V.sub.o2] and their frequency spectrums. The output current waveform and its spectrum at [f.sub.0] = 100 kHz is depicted in Figure 8. Tuning of experimental and theoretical FO is shown in Figure 9, where [I.sub.B1] and [I.sub.B2] are equal and were adjusted from 100 [micro]A to 500 [micro]A. The range of FO controlled from 27 kHz-131 kHz was obtained. Figure 10 shows simulated dependence of output amplitudes [V.sub.O1] and [V.sub.O2] on FO. It can be clearly seen that the ratio of amplitudes [V.sub.O1] and [V.sub.O2] is quite constant on the tuning of FO if [I.sub.B1] and [I.sub.B2] are simultaneously tuned as predicted in (10). As stated above, VDCC consists of operational transconductance amplifier (OTA) where it is well known that the BJT OTA gives the linear range if input voltage is lower than 2[V.sub.T] ([congruent to]52 mV). With the result in Figure 10, it is found that the amplitude of output voltages which dropped on input voltage of OTA is close to linear range of OTA. This implies that sinusoidal output waveforms provide good THD. However, at high value of bias current, the deviation of amplitude ratio of [V.sub.o1] and [V.sub.o2] obviously appears. This phenomenon results from the fact that the increment of bias current will decrease the value of parasitic resistance. Therefore, the amplitude of [V.sub.o1] and [V.sub.o2] is slightly different as analyzed in (19). The measured phase difference between the two outputs, [V.sub.o1] and [V.sub.o2], is illustrated in Figure 11.

6. Comparison with Recent Quadrature Oscillators

A comparison between the proposed quadrature oscillator and recent quadrature oscillator published in scientific journals is shown in Table 1. The terms that will be taken into account are as follows: the used active building block (ABB), number of active and passive element, the way to tune FO and CO, amplitude of the quadrature output waveforms during tuning process, the used ABB without multiple or extra terminals, additional current output with high impedance, the connection of capacitors, and the way to test the circuit.

7. Conclusion

In this contribution, the quadrature sinusoidal oscillator using voltage differencing current conveyor as active element is presented. The proposed circuit comprises two VDCCs, two resistors, and two grounded capacitors. The proposed oscillator provides quadrature voltage output and a high impedance current output. The frequency of oscillation can be electronically tuned without affecting the condition of oscillation. During tuning of the frequency of oscillation, the amplitude of the quadrature output voltages [V.sub.o1] and [V.sub.o2] is almost constant with slight differences due to the effect of the parasitic resistances and capacitances of the VDCC. The experimental results using VDCC constructed from commercially available ICs confirm the performance of the theoretical analysis.

Conflicts of Interest

The authors declare that they have no conflicts of interest.

https://doi.org/10.1155/2017/8575743

Acknowledgments

Research described in this paper was financially supported by King Mongkut's Institute of Technology Ladkrabang (KMITL) and by National Research Council of Thailand (NRCT), Grant no. A118-59-028.

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Den Satipar, (1) Pattana Intani, (1) and Winai Jaikla (2)

(1) Department of Electrical Engineering, Faculty of Engineering, Pathumwan Institute of Technology, Bangkok 10330, Thailand

(2) Department of Engineering Education, Faculty of Industrial Education and Technology, King Mongkut's Institute of Technology Ladkrabang, Bangkok 10520, Thailand

Correspondence should be addressed to Winai Jaikla; winai.ja@hotmail.com

Received 13 March 2017; Revised 16 May 2017; Accepted 25 May 2017; Published 21 June 2017

Academic Editor: Jit S. Mandeep

Caption: Figure 1: VDCC: (a) circuit symbol of VDCC; (b) equivalent circuit.

Caption: Figure 2: Internal construction of CMOS VDCC [10].

Caption: Figure 3: VDCC (without dual W terminal) constructed from commercially available ICs.

Caption: Figure 4: Proposed quadrature oscillator.

Caption: Figure 5: Measurement of output voltages and their spectrums at [f.sub.0] = 50 kHz.

Caption: Figure 6: Measurement of output current and its spectrum at [f.sub.0] = 50 kHz.

Caption: Figure 7: Measurement of output voltages and their spectrums at [f.sub.0] = 100 kHz.

Caption: Figure 8: Measurement of output current and its spectrum at [f.sub.0] = 100 kHz.

Caption: Figure 9: Tuning of experimental and theoretical FO by adjusting bias current.

Caption: Figure 10: Dependence of amplitudes of [V.sub.O1] and [V.sub.O2] on FO.

Caption: Figure 11: The measured phase difference of [V.sub.O1] and [V.sub.O2].
Table 1: Comparison results of this work and recent works.

                                             Electronic     Equal
                                              tune of      ampli-
                                                 FO         tudes
                                              without      during
                        Number   Number of   affecting    frequency
Ref            ABB      of ABB     R + C         CO        tuning

[23]          VDCC        1        2 + 2         No          No
[24]          VDCC        1        2 + 2        Yes          No
[25]          VDCC        2        2 + 2        Yes          No
[26]         CG-VDCC      1        0 + 2        Yes          Yes
[31]         CCCCTA       1        2 + 2        Yes          No
[32]         CCCCTA       2        2 + 2        Yes          No
[33]        CCII & BF     3        4 + 2         No          No
[34]          CCII        3        2 + 2        Yes          No
[35]          CDTA        2        0 + 3        Yes          No
[36]          CFOA        2        2 + 2         No          No
[37]          CFOA        2        3 + 2         No          No
[38]        DD-DXCCII     1        3 + 2         No          No
[39]          MDVCC       1        2 + 2         No          No
[40]         DVCCTA       1        3 + 2        Yes          No
[41]         FBVDBA       1        1 + 2         No          No
[42]          OTRA        2        3 + 3         No          No
[43]         MVDVTA       1        1 + 2         No          No
This work     VDCC        2        2 + 2        Yes          Yes

                             Providing
                             additional
            No need of   sinusoidal current
             multiple     output with high    Grounded   Experimental
Ref         output ABB       impedance         C only      results

[23]            No              Yes             Yes           No
[24]            No               No             Yes          Yes
[25]            No              Yes             Yes           No
[26]            No               No             Yes           No
[31]            No              Yes             Yes           No
[32]            No              Yes             Yes           No
[33]           Yes               No             Yes          Yes
[34]           Yes               No             Yes           No
[35]            No              Yes             Yes           No
[36]           Yes               No             Yes          Yes
[37]           Yes               No             Yes          Yes
[38]            No               No             Yes           No
[39]           Yes               No             Yes           No
[40]            No              Yes             Yes           No
[41]            No               No             Yes          Yes
[42]           Yes               No              No          Yes
[43]            No               No             Yes           No
This work      Yes              Yes             Yes          Yes
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Title Annotation:Research Article
Author:Satipar, Den; Intani, Pattana; Jaikla, Winai
Publication:Journal of Electrical and Computer Engineering
Date:Jan 1, 2017
Words:4596
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