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Electronically Adjustable Emulator of the Fractional-Order Capacitor.

I. Introduction

The research in the area of fractional-order systems and circuits is an attractive topic for many scientific groups around the world [1], [2]. Compared to the integer-order systems, fractional-order systems can expand the possibilities in designing of different systems in various scientific areas, e.g., in measurement of biological samples [3]-[6], design of control systems [7]-[9], measurement techniques of various signals [10], [11], electronics [12], [13], and agriculture [14].

Recently, many research teams have focused on the design of the FOEs (Fractional-Order Elements) and its use. The FOE represents the non-integer order passive element when the slope of the attenuation of its impedance is 20 x [alpha] dB/decade, where [alpha] is a real number in range 0 < [alpha] < 1 [15]. The phase shift of the FOE is 90 x [alpha] degrees [15]. The most often designed FOE is FOC (Fractional-Order Capacitor) element with character between a capacitor and resistor [15]--[17]. The resulting impedance of FOC is then given by [Z.sub.FOC](s) = 1/([s.sup.[alpha]] x [C.sub.[alpha]]), where s is Laplacian operator and Ca is called as pseudo-capacitance in Farad/[sec.sup.1-[alpha]] [17], [18]. Next type of the FOE is FOI (Fractional-Order Inductor), where its impedance is Z(s) = [s.sup.[alpha]] x [L.sub.[alpha]], where the [L.sub. [alpha]] is called as pseudo-inductance in Henry/[sec.sup.1-[alpha]] [19].

FOC is not commercially available element nowadays [16]. However, FOC can be approximated by suitable RC (Resistor-Capacitor) ladder structure with selected parameters. There are several types of the most commonly used RC ladder structures: Foster I, Foster II, Cauer I, and Cauer II [17]. The calculation of the values of resistors and capacitors of the RC structure is based on the selected approximation of the [s.sup.[alpha]]. The CFE (Continued Fraction Expansion) and Oustaloup's approximation are most commonly used approximations for the FOC design [8], [17]-[19]. The advantage of this method is easy usage of the proposed RC structures approximating the FOC in any circuit structure (oscillator, filter, etc.) instead of conventional capacitor [20]-[22]. One of the drawbacks of this design method is the limitation of frequency band of the approximation validity, which depends on the number of sections of the proposed RC structure. Another disadvantage is that for each value of [alpha] a new RC structure with recalculated values of the passive parts must be arranged.

A design of a novel controllable FOC emulator is introduced in this paper. The FOC emulator is designed based on 5th-order of the RC ladder structure (type Foster I) with Oustaloup's approximation, where the passive parts are replaced with the subcircuits with electronically controllable parameters. The proposed circuit offers electronic control of its order and shifting of the frequency band of the approximation validity without disturbing each other. In comparison with passive FOC, only one structure is used for realization of different values of the order of FOC emulator and approximation types (Oustaloup, CFE, etc.). All passive parts in the topology have a constant value. Another advantage is that the frequency band of the approximation validity can be easily shifted. Only in [19], scientists present similar solutions of the active FOC emulator. In comparison with [18], the circuit presented in this paper provides the FOC order and approximation validity frequency band controlling. The fractional-order low-pass and high-pass filters with controllable characteristics are designed using our proposed controllable FOC emulator.

II. Properties of Used Active Elements

The proposed electronically adjustable FOC (Fractional-Order Capacitor) emulator consists of structure with two types of active elements. The first type of active element is OTA (Operational Transconductance Amplifier) with two voltage inputs and one current output [23]. The schematic symbol of this element is shown in Fig. 1(a). The function of the OTA element is described by the relation [I.sub.OUT] = [g.sub.m] x ([V.sub.IN+] - [V.sub.IN-]), where the parameter gm represents the transconductance. If necessary, the number of the current outputs of OTA can be easily extended. The second type of the active element used in FOC emulator is VDCC (Voltage Differencing Current Conveyor) [24]. The schematic symbol and internal block conception are depicted in Fig. 2. It can be seen that VDCC consists of one OTA and CCII+/- (Second Generation Current Conveyor). The relations between VDCC terminals are as follows: [I.sub.Z] = [g.sub.m] X ([V.sub.P] - [V.sub.N]), [I.sub.P] = [I.sub.N] = 0, [V.sub.X] = [V.sub.Z], [I.sub.WP] = -[I.sub.WN] = -[I.sub.X] [24].

The proposed fractional-order filter is designed using one CCTA (Current Conveyor Transconductance Amplifier) [25] and auxiliary DO-CF (Dual-Output Current Follower). The schematic symbol and internal block concept of the CCTA are shown in Fig. 3. It can be seen that CCTA contains one CCII+/- and BOTA (Balanced-Output Transconductance Amplifier). The function of the CCTA is described by the following equations: [I.sub.OUT+] = -[I.sub.OUT-] = [g.sub.m] x [V.sub.Z+], [I.sub.Y] = 0, [V.sub.X] = [V.sub.Y], and [I.sub.Z+] = -[I.sub.Z-] = [I.sub.X]. [25]. The DO-CF schematic symbol is shown in Fig. 1(b). The function of the DO-CF is described by following equation: [I.sub.OUT+] = -[I.sub.OUT-] = [I.sub.IN].

III. Design of the Electronically Controllable FOC

The FOC is approximated by 5th-order RC structure in our design. In this case, the Foster I type topology is used with floating resistors and capacitors as is shown in Fig. 4(a). The impedance of the Foster I structure is described by the following equation [18]

[mathematical expression not reproducible]. (1)

The values of the particular resistors and capacitors were calculated using Oustaloup's approximation (performed in the MATLAB) [8] for the selected values of a, central frequency [f.sub.CENTRAL] ([f.sub.CENTRAL] represents the center of the band, where the approximation is valid), and the frequency band of the approximation validity and equivalent capacitance [C.sub.eq] of the FOC. The equivalent capacitance [C.sub.eq] at the angular frequency [[omega].sub.0], which is, in this case, equal to 2 x [pi] x [f.sub.CENTRAL], is related to the so-called pseudo-capacitance [C.sub.[alpha]] of FOC by the formula [C.sub.[alpha]] [C.sub.eq] x [w.sub.0.sup.1-[alpha]] [18]. The obtained values of the capacitors and resistors from the proposed topology in Fig. 4(a) with five values of a are summarized in Table I.

Figure 4 (b) represents electronically controllable FOC emulator. In the RC structure (see Fig. 4 (a)), the passive parts are replaced by the subcircuits with electronically controllable active elements.

The resistors are replaced by BOTA elements connected as it is shown in Fig. 5 [6]. The value of the equivalent resistor is calculated as follows: [R.sub.new] = 1/[g.sub.m_R]. It is obvious that the value of the resistor is electronically controllable by changing the value of the parameter [g.sub.m_R].

The capacitors in the RC structure are replaced by the capacitor multipliers that are designed by VDCC [26]. The design of the capacitor multiplier is depicted in Fig. 6. The value of the new capacitor is calculated by: [C.sub.new] = C x R x [g.sub.m_c], where C is original value of capacitance connected to the terminal X of the VDCC, R is auxiliary resistor, and [g.sub.m_c] is transconductance. From the equation, it is observed that the value of the capacitance is electronically controllable by [g.sub.m_c].

Note that the values of the capacitors C and auxiliary resistors R for all capacitance multipliers in the topology are constant.

The proposed circuit enables control of the order of the FOC [alpha] and shift of the frequency band of the approximation validity. The value of [alpha] can be changed by adjusting all of the transconductances as in Fig. 4(b) to obtain the resistance and capacitance values according to Table I. The shifting of the frequency band of the approximation validity of the proposed FOC emulator is possible by changing the values of the controllable capacitors. When all the capacitances decreasing &-times, the frequency band shifts to k-times higher values and obviously the central frequency [f.sub.CENTRAL] also increases &-times.

IV. Simulation Results

The features of the designed controllable FOC were verified in the OrCAD PSpice with behavioral models of the active elements.

The OTA (BOTA) elements are implemented by 3rd-level of the UCC (universal Current Conveyor) simulation model with external resistor connected to its low impedance terminal X [27]. The value of the resistor represents the value of the transconductance [g.sub.m] = 1/[R.sub.X]. In case of the resistor emulator implemented by UCC, the new value of resistor is described by [R.sub.NEW] = 1/[g.sub.m_R] = [R.sub.X].

The implementation of the VDCC is based on internal block conception previously presented in Fig. 2(b). The OTA is again implemented by UCC [27] active element. The 3rd-level of the simulation model is also used for the implementation of CCII+/-.

The proposed circuit is simulated with the following values of the parameters: central frequency of the approximation validity frequency band [f.sub.CENTRAL] = 10 kHz, validity of the approximation from 100 Hz to 1 MHz (4 decades theoretically), equivalent capacitance of the FOC [C.sub.eq] = 20 nF, and five values of [alpha] from 0.25 to 0.75 (Table II). The values of passive parts of all capacitance multipliers in the 5th-order structure have constant and identical values for all selected [alpha] (R = 2 k[ohm] and C = 20 nF).

Table II summarizes all the values of the particular parts of the proposed controllable FOC for the five values of a. The values are calculated based on the values in Table I and the equations describing resistor emulator and capacitance multiplier as mentioned above. It can be seen that for changing the parameter [alpha], all parameters, except R and C, must be changed.

Figure 7(a) and Figure 7(b) show the obtained non-ideal simulation results (solid lines) of the designed circuit in comparison with ideal results (dashed lines). The values of [alpha] obtained from non-ideal simulations based on the magnitude slope values around the central frequency are: 0.72, 0.58, 0.49, 0.39, and 0.247. It is derived that non-ideal results are very close to the ideal ones. The value of the circuit impedance [absolute value of Z] is 796 [ohm] at the central frequency for all values of [alpha]. From both ideal and non-ideal phase responses, it is obvious that the approximation validity bandwidth decreases for increasing [alpha]. The most significant differences can be seen for the results of the FOC with [alpha] = 0.75. It is caused by unsuitable values of components with respect to parameters of the used UCC. The differences at high and low frequencies are given by bandwidth limitations and parasitic properties of the used models of the active elements. That also applies for the shifting of the frequency band of the approximation validity.

The designed circuit also provides controllability of approximation validity frequency band. It is possible by changing the values of parameters [g.sub.m_C1] to [g.sub.m_C5] of the capacitance multipliers. For demonstration of the frequency tuning, the circuit with [alpha] = 0.4 was selected. The circuit was tested for five values of [f.sub.CENTRAL]. The used values of the circuit parameters for frequency tuning are summarized in Table III. Figures 8(a) and 8(b) show the magnitude and phase responses of the circuit. Obtained values of [f.sub.CENTRAL] from non-ideal simulation results are: 3.1 kHz, 6.1 kHz, 12 kHz, 24.4 kHz, and 48 kHz.

V. Application of the Designed Circuit in the Filter

As mentioned above, FOC can be used for fractional-order frequency filter design by replacing the conventional capacitor in the structure. The order of the fractional-order filter is described according to the formula (n + [alpha]), where n is positive non-zero integer number [20]-[22]. The slope of attenuation of the fractional-order filter is described by the following equation: 20 x (n + [alpha]) dB/decade.

Figure 9 represents the proposed filtering topology. It consists of one CCTA and one auxiliary DO-CF as active elements, whose properties are described above. In the structure, capacitor [C.sub.[alpha]] is replaced by controllable FOC structure presented above. The proposed filter provides the FLPF (Fractional-Order Low-Pass Filter) and FHPF (Fractional-Order High-Pass Filter) responses.

The general transfer function of FLPF is given by [28]

[mathematical expression not reproducible], (2)

where [[omega].sub.o] = 2 x [pi] x [f.sub.o] [rad/s] is used for frequency shifting the cut-off frequency to the required value [f.sub.0]. The values of [K.sub.1] = 1, [K.sub.2] = 1.008 x [[alpha].sup.2] + 0.2867 x [alpha] + 0.2366, and [K.sub.3] = 0.2171 x [alpha] + 0.7914 are adopted from [28]. They are found to obtain maximally flat (Butterworth-like) magnitude frequency characteristic of the filter.

The denominator of the proposed fractional-order filter in terms of circuit elements is given by

D = [s.sub.1+[alpha]] + s 1/[C.sub.[alpha]][R.sub.x] + [g.sub.m]/[C.sub.[alpha]][C.sub.2][R.sub.X]. (3)

The values of the resistor [R.sub.X] and transconductance [g.sub.m] of the proposed filter are calculated by the following equations that stem from the comparison of (3) with denominator of (2):

[R.sub.X] = [K.sub.1]/[K.sub.2][w.sup.[alpha].sub.0][C.sub.[alpha]], (4)

[g.sub.m] = [K.sub.3][[omega].sub.0][C.sub.2]/[K.sub.2]. (5)

The PSpice simulations with behavioral models of the active elements were used for verification of the filter features. The DO-CF is implemented by 3rd-level of the CCII+/- simulation model. For CCTA implementation, CCII+/- and BOTA active elements connected as shown in Fig. 3 are used. The BOTA element is implemented as mentioned in Section IV. The simulations of the filter were performed with the following values of the parameters: pole frequency [f.sub.0] = [omega]0/(2 x [pi]) = 10 kHz, equivalent capacitance of FOC at 10 kHz was [C.sub.eq] = 20 nF, pseudo-capacitance [C.sub.[alpha]] = [C.sub.eq] x [[omega].sub.0.sup.1-[alpha]], and ordinary capacitor value [C.sub.2] = 20 nF. The fractional-order filter was tested for three values of the filter order (1.25, 1.5, and 1.75), which is controlled by changing the parameters of the FOC emulator presented in Fig. 4(b). The corresponding values of [alpha] are 0.25, 0.5, and 0.75. The used values of the filter parameters are listed in Table IV.

The magnitude responses of the FLPF and FHPF for three selected values of a are depicted in Fig. 10(a) and Fig. 10(b). The values of the order of the FLPF obtained from slopes of the non-ideal characteristics in Fig. 10(a) are as follows: 1.23 (slope of attenuation 24.6 dB/decade), 1.47 (slope of attenuation 29.36 dB/decade), and 1.72 (slope of attenuation 34.4 dB/decade). The values of the order of the FHPF (see Fig. 10(b)) from the non-ideal simulations are: 1.247 (slope of attenuation 24.94 dB/decade), 1.48 (slope of attenuation 29.61 dB/decade), and 1.67 (slope of attenuation 33.4 dB/decade). Obtained values are in good agreement with the respective theoretical values 1.25, 1.5, and 1.75. The differences are caused by complexity of the proposed circuit (FOC emulator). The bandwidth limitations of the non-ideal models of the active elements are seen at high frequencies.

VI. Conclusions

The design of the controllable fractional-order capacitor (Foe) emulator and its application is presented in this paper. The circuit provides control of the order a and frequency band of the constant phase without disturbing each other. The FLPF and FHPF with controllable order are designed for verification of the FOC emulator function. The proposed filter also provides frequency tuning by changing the values of the [R.sub.X] and [g.sub.m] as seen from (4), (5). The frequency tuning of the filter is not included in this paper. Also, the presented study can be extended for other integer-order approximations of the fractional-order capacitive impedance as the Oustaloup's one. The order of the approximation can be varied and other RC topologies than Foster I can be utilized.

http://dx.doi.org/10.5755/j01.eie.25.6.24823

Manuscript received 21 January, 2019; accepted 4 August, 2019.

This article is based upon work from COST Action CA15225, a network supported by COST (European Cooperation in Science and Technology). Research described in this paper was financed under the National Sustainability Program by a grant (No. LO1401) from the Ministry of Education, Youth and Sports and by a grant (No. LTC18022) from the General Secretariat for Research and Technology (GSRT) and the Hellenic Foundation for Research and Motivation (HFRI). For the research, infrastructure of the SIX Center was used.

Conflicts of Interest

The authors declare that they have no conflicts of interest.

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Jan Dvorak (1), *, David Kubanek (1, Norbert Herencsar (1), Aslihan Kartci (1), Panagiotis Bertsias (2)

(1) Faculty of Electrical Engineering and Communication, Brno University of Technology, Technicka 12, 61600, Brno, Czech Republic

(2) Department of Physics, University of Patras, GR-26504, Rio Patras, Greece dvorakjan@feec.vutbr.cz

Caption: Fig. 1. Schematic symbols: (a) Operational Transconductance Amplifier (OTA); (b) Dual-Output Current Follower (DO-CF).

Caption: Fig. 2. Voltage Differencing Current Conveyor (VDCC): (a) Schematic symbol; (b) Internal block conception.

Caption: Fig. 3. Current Conveyor Transconductance Amplifier (CCTA): (a) Schematic symbol; (b) Internal block conception.

Caption: Fig. 4. The 5th-order structures approximating the FOC (Fractional-Order Capacitor): (a) Passive RC topology; (b) Electronically adjustable topology.

Caption: Fig. 5. The electronically controllable floating resistor designed with BOTA (Balanced Output Transconductance Amplifier).

Caption: Fig. 6. The electronically adjustable floating capacitor designed by capacitance multiplier that uses the VDCC active element.

Caption: Fig. 7. Simulation results of the proposed controllable FOC for five selected values of [alpha] at central frequency 10 kHz: (a) Magnitude responses; (b) Phase responses.

Caption: Fig. 8. Tuning of the frequency band of approximation validity of FOC emulator with [alpha] = 0.4: (a) Magnitude responses; (b) Phase responses.

Caption: Fig. 9. Topology of the designed filter containing an electronically controllable FOC.

Caption: Fig. 10. Simulation results of the designed fractional-order filter with behavioralmodels. Magnitude responses of: (a) FLPF; (b) FHPF for three values of the fractionalorder at frequency [f.sub.0] = 10 kHz.
TABLE I. VALUES OF THE FOSTER I TYPE RC TOPOLOGY WITH FIVE DIFFERENT
VALUES OF ALPHA.

[alpha][-]                  0.75    0.6     0.5     0.4     0.25
[C.sub.eq] [nF]                             20
[C.sub.[alpha]] [[micro]F   0.32    1.7     5.01    15.1    79.4
/[sec.sup.1-[alpha]]]

[R.sub.0] [k[ohm]]          0.025   0.052   0.08    0.126   0.252
[R.sub.1] [k[ohm]]          0.03    0.059   0.082   0.106   0.129
[R.sub.2] [k[ohm]]          0.136   0.201   0.23    0.243   0.218
[R.sub.3] [k[ohm]]          0.560   0.622   0.59    0.516   0.35
[R.sub.4] [k[ohm]]          2.421   1.986   1.546   1.111   0.564
[R.sub.5] [k[ohm]]          22      9.692   5.431   2.921   1.004

[C.sub.l][nF]               26.6    11.8    7.7     5.5     3.9
[C.sub.2][nF]               36.9    21.8    17.4    15.03   14.6
[C.sub.3][nF]               56.7    44.5    42.8    44.6    57.3
[C.sub.4][nF]               82.75   87.8    102.9   130.7   224
[C.sub.5][nF]               57.5    113.6   184.9   313.6   794.2

TABLE II. SUMMARIZATION OF THE DESIGNED TOPOLOGY
PARAMETERS FOR FIVE VALUES OF ALPHA.

[alpha][-]                   0.75     0.6     0.5     0.4    0.25

C[nF]                                         20
R[k[ohm]]                                      2
[absolute value of Z] @                      0.796
[f.sub.CENTRAL] [k[ohm]]
[C.sub.eq] [nF]                               20
[C.sub.[alpha]] [[micro]F/   0.32     1.7    5.01    15.1    79.4
[sec.sup.1-[alpha]]]

1/[g.sub.m_R0] [k[ohm]]      0.025   0.052   0.08    0.126   0.252
1/[g.sub.m_R1] [k[ohm]]      0.03    0.059   0.082   0.106   0.129
1/[g.sub.m_R2] [k[ohm]]      0.136   0.201   0.23    0.243   0.218
1/[g.sub.m_R3] [k[ohm]]      0.560   0.622   0.59    0.516   0.35
1/[g.sub.m_R4] [k[ohm]]      2.421   1.986   1.546   1.111   0.564
1/[g.sub.m_R5] [k[ohm]]       22     9.692   5.431   2.921   1.004

1/[g.sub.m_C1] [k[ohm]]       1.5    3.39     5.2    7.27    10.26
1/[g.sub.m_C2] [k[ohm]]      1.08    1.83     2.3    2.66    2.75
1/[g.sub.m_C3] [k[ohm]]      0.71    0.89    0.94     0.9     0.7
1/[g.sub.m_C4] [k[ohm]]      0.48    0.46    0.39    0.31    0.18
1/[g.sub.m_C5] [k[ohm]]      0.69    0.35    0.22    0.13    0.05

TABLE III. VALUES OF THE DESIGNED CIRCUIT PARAMETERS
for frequency control WITH ALPHA = 0.4.

[f.sub.CENTRAL] [kHz]        2.5      5      10      20      40

C[nF]                                        20
R[k[OMEGA]]                                   2
[absolute value of Z]                       0.796
@[f.sub.CENTRAL] [k[ohm]]
[C.sub.eq] [nF]                              20
[C.sub.[alpha]] [[micro]F                   15.1
/[sec.sup.1-[alpha]]]

1/[g.sub.m_C1] [k[ohm]]     1.82    3.63    7.27    14.54   29.09
1/[g.sub.m_C2] [k[ohm]]     0.67    1.33    2.66    5.32    10.64
1/[g.sub.m_C3] [k[ohm]]     0.23    0.45     0.9     1.8     3.6
1/[g.sub.m_C4] [k[ohm]]     0.078   0.16    0.31    0.62    1.24
1/[g.sub.m_C5] [k[ohm]]     0.033   0.065   0.13    0.26    0.52

TABLE IV. THE FILTER PARAMETERS FOR ORDER CHANGING.

Theoretical values                               1.25    1.5    1.75
of the filter order

[C.sub.[alpha]] [[micro]F/[sec.sup.1-[alpha]]]   79.4    5.01   0.32
[C.sub.2] [nF]                                           20
[R.sub.X] [K[OMEGA]]                             2.14    1.26   0.78
[R.sub.gm] = 1/[g.sub.m] [k[OMEGA]]              0.349   0.56   0.85
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Author:Dvorak, Jan; Kubanek, David; Herencsar, Norbert; Kartci, Aslihan; Bertsias, Panagiotis
Publication:Elektronika ir Elektrotechnika
Date:Dec 1, 2019
Words:4804
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