Efficiency increase of switched mode power supply through optimization of transistor's commutation mode/Galios saltiniu perjungimo busenos efektyvumo didinimas optimizuojant tranzistoriu perjungimo busenas.
Nowadays, the main stream in the field of power semiconductor devices is concentrated on continual improvements of static, dynamic, thermal properties. This fact is reflected in research and application of new materials (SiC, GaN), which should be suited for semiconductors manufacture. Also new IEC standards are being constantly tightened, what is in the final result reflected in the designing of "EcoSmart" and "green" solutions. One of the merits is efficiency of power supplies, which has to be always as higher as possible. There are several ways how to eliminate almost all of the losses of power semiconductor devices, whereby one way is to utilize soft-switching technique, second way is to utilize the progressive semiconductor structures. Nevertheless to reach a compromise between switching frequency, efficiency and output power, the optimization of parameters, which influence transistor's commutation mode, is necessary. The first step in optimization consists in commutation mode selection. The second step is checking out general parameters of the selected mode e.g. dead-time, slope grows of current/voltage, gate resistor, auxiliary capacitance to find influence on switching losses at various switching frequencies. A perfect way of investigation could be the experimental analysis; nevertheless simulation analysis should demonstrate an overview of acceptable semiconductor switching losses for the selected transistor and target application.
Energy balance of commutation process of power transistor
Due to existence of feedback between rise/fall of transistor's voltage UDS and fall/rise of transistor's current ID the generation of power loss come into being. The analytical expression for total amount of power loss which is generated during one switching cycle is
P.sub.TOT] = 1/T [W.sub.ON] + 1/T [W.sub.COND] + 1/T [W.sub.OF] + 1/T [W.sub.OFF], (1)
where [W.sub.ON]--energy absorbed during turn--on process; [W.sub.COND]--energy absorbed during conduction time; [W.sub.OF]--energy absorbed during turn--of process; [W.sub.OFF]--energy absorbed during off--state; T--time period.
During computation of each part of losses next equations have been used.
[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] (2)
where [i.sub.P](t)--time function of transistor's current; [u.sub.P](t)--time function of transistor's voltage; [T.sub.Z1]--sequence of sample at the begin of transistor's turn-on/turn-off process; [T.sub.Z2]--sequence of sample at the end of transistor's turn-on/turn-off process; [I.sub.P][i]--ith sample of transistor's current; [U.sub.P][i]--ith sample of transistor's voltage; [DELTA]T--sampling time.
To find best commutation mode for selected transistor, the investigation is first executed by simulation analysis of most well known switching technique, which are hard switching, ZVS and ZCS.
Simulation analysis of selected commutation techniques
The aim of this chapter is to compare and evaluate processes during switching action of power transistor at various settings of switching mode parameters. Because of that each commutation mode requires specific behavior of circuit, the circuit simulation models were adapted to fulfill this requirement and meet the reality and authenticity of target application. Next figures show principal schematics of testing circuits which have been used in simulation environment.
The simulation analysis of hard switching technique is realized by circuit that is shown on Fig. 1, which represents replacement scheme for the investigation of dynamic characteristics of power transistors or diodes. Thus in this way it is possible to make parametrical analysis with the change of components which are influencing dynamic characteristics [2, 3, 5, 11].
[FIGURE 1 OMITTED]
Parameters of simulation: [U.sub.IN] = 325 V, [I.sub.LOAD] = 10 A, [R.sub.GATE] = 33 [ohm], slope of current rise di/dt = 250 A/us, [f.sub.SW] = 100 kHz.
The results of hard switching mode are listed in Table 1. The amount of turn--on losses is highly dependent on type of [D.sub.NULL]. Turn--of losses are mostly dependent on dynamic behavior of transistor or/and on gate drive circuit.
The simulation analysis of zero voltage switching technique is realized by circuit that is shown on Fig. 2. The main leg consists of transistors which were subjected to analysis. The load is presented by series resonant circuit ([C.sub.R], [L.sub.R], and [R.sub.LOAD]). The only part of power losses in ZVS commutation mode are turn--of losses as turn--on losses are null due to switching of transistor at zero voltage.
[FIGURE 2 OMITTED]
During simulation experiment of ZVS turn--of process the auxiliary capacitance has been connected in parallel to analyzed transistor for securing the ZVS conditions. For parametric evaluation of ZVS turn--of process variable parameter were dead time ([t.sub.D]) and auxiliary capacitance ([C.sub.OSSAUX]).
Parameters of simulation: Constant parameters: [U.sub.IN] = 325 V, [I.sub.LOAD] = 10 A, [R.sub.GATE] = 20 [ohm], [f.sub.SW] = 100 kHz. Variable parameters: [t.sub.D] = 300ns, 500ns, [C.sub.OSSAUX] = 0nF, 1nF
The results of ZVS mode are listed in Table 2. It can be seen that the value of turn--of losses is highly dependent on both variable parameters. Higher value of auxiliary capacitance is limiting the rise of transistor's voltage slope and longer dead time secures more time to charge/discharge the internal/auxiliary capacitances.
Simulation analysis of ZCS switching technique has been performed through the use of circuit which is show on Fig. 3. The resonant components ([L.sub.R], [C.sub.R]) form the necessary conditions for generating waveforms in ZCS commutation mode. The load is presented by fast voltage rectifier (D1, D2, D3, and D4) and by the load resistance ([R.sub.LOAD]). If rectifier is replaced by resistance, the circuit would work as an series resonant inverter.
[FIGURE 3 OMITTED]
Parameters of simulation: Constant parameters: [U.sub.IN] = 325 V, [I.sub.LOAD] = 10 A; [R.sub.GATE] = 22 [ohm], [f.sub.SW] = 100 kHz. Variable parameter: [t.sub.D] = 300ns, 500ns, 1[micro]s
Table 3 is showing results from parametric simulation experiment of ZCS turn--on process. In any case of dead time setting the turn--on losses are almost the same. Therefore it could be said, that dead time is not influencing the amount of turn on losses, and existing difference should be caused by simulation error. Opposite situation is visible at investigation of turn--of power losses. Value of this loss is not in linear relationship to dead time, whereby the lowest value of losses occurs at the highest value of dead time. It is also generally well known that ZCS is not good option for unipolar transistor structure, due to existence of high value of internal capacitances [1, 4, 6].
Fig. 4. is showing comparison of absorbed energy during one switching period of transistor at various commutation modes.
[FIGURE 4 OMITTED]
These waveforms were prepared by OrCAD_PSpice simulation tool, and are valid for best conditions of each commutation mode (ZVS: [t.sub.D] = 500 ns, [C.sub.OSSAUX] = 1 nF, ZCS: [t.sub.D] = 1 us). It has to be noted that, waveform is showing also absorbed energy during conduction interval. The amount of switching losses is from begin to the end of turn--on, or turn--of process.
Utilization of optimized commutation mode at selected SMPS topology
The well-known PWM hard switching converters are characterized by low efficiency due to high value of power losses that are caused by high switching frequency operation. The candidate topology for the current fast-switching applications achieving high efficiency is represented by resonant converters. The resonant converters are well-known due to their high efficiency and low EMI noise. The perspective resonant topology is nowadays the LLC resonant converter (Fig. 5). The benefit of the LLC resonant converter is a narrow switching frequency range with a light load and ZVS capability with even no load [7-10]. It is well-known that a LLC converter is a multiresonant type of converter. It could be working at three different types of operation (Fig. 5). Each operating state is dependent on DC--gain characteristic of the LLC converter. Region 1 and Region 2 are characterized by ZVS operating conditions. The operation of the converter in Region 3 is not recommended due to the ZCS conditions. For operation of the converter with constant DC voltage, it is recommended to operate at the boundary between Region 1 and Region 2. The region 2 is recommended for the operation when reduced DC-supply voltage occurs at the input of the converter. A detailed character of operation in each region is described at [8-10].
For evaluation of optimized commutation mode and for comparison of results with non-optimized settings we have focused only on the most complex operation, which is in the Region 2. Depending on the state of the power switches T1 and T2, the operation of the LLC converter in Region 2 can be divided into six time intervals per cycle.
[FIGURE 5 OMITTED]
Fig. 6 shows the relationship of currents and voltages in the LLC converter during each interval. Note that for operation of the LLC converter in Region 1 the interval t1 [right arrow] t2 will disappear. The investigation of influence of optimized commutation mode on efficiency of converter was done by utilization of OrCAD_PSpice software. The results of simulation analysis are shown on Fig. 7.
[FIGURE 6 OMITTED]
Parameters of simulation: Constant parameters: input voltage of LLC, [U.sub.IN] = 325 V; output voltage of LLC, [U.sub.OUT] = 60V; switching frequency of LLC, [f.sub.SW] = 100 kHz; output power of LLC, [P.sub.OUT] = 1500W; resonant circuit parameters: [L.sub.R] = 6,6 [micro]H, CR= 100 nF, [L.sub.M] = 36 [micro]H. Variable parameters: deadtime, [t.sub.D] = 300ns, 500ns; transistor's auxiliary capacitance, [C.sub.OSSAUX] = 0nF, 1nF.
[FIGURE 7 OMITTED]
From the results above, when operating transistor in hard switching mode it could be said that turn--of losses can be reduced by utilization of faster device. The result of ZVS analysis is confirmation of benefits using unipolar structures in this commutation mode, namely IPW60R165CP, which due to good static and dynamic parameters has showed very low switching losses. Turn--of losses in ZVS mode has showed obvious dependency on variable parameters [C.sub.OSSAUX] and [t.sub.D], where increase of [t.sub.D] and increase of [C.sub.OSSAUX] had decreased total power losses markedly. At settings of [C.sub.OSSAUX] = 1nF and [t.sub.D] = 500ns the transistor IPW60R165CP has showed the lowest value of power losses. The analysis of ZCS technique has showed that by its utilization the both components of switching losses could be eliminated. Ideal use is for IGBT structure. ZCS switching mode is not recommended for unipolar structures due to their high value of parasitic capacitances. The best results has occurred at setting [t.sub.D] = 1us. This value of deadtime is very high for high frequency applications; therefore the results of power losses in this case are not directive.
Comparing losses of MOSFETs the total power losses in ZCS mode rose up by 37% in the case of IPW60R165CP comparing to ZVS mode with [C.sub.OSS(AUX)] = 1nF and [t.sub.D] = 500ns.
The investigation of commutation mode terminates into verification of optimal settings of selected commutation technique (ZVS) through simulation analysis of selected topology of SMPS, which is LLC resonant converter. During simulation experiments at maximum load of LLC converter (1500 W), the important parameters such dead time and auxiliary capacitance of transistor were changed. The influence of these parameters were monitored and reflected on efficiency of converter. As can be seen the optimization of commutation mode caused increase of efficiency by 1,25% comparing to non--optimized solution of commutation mode. Thus in such way it is possible to increase efficiency of SMPS almost in every application.
The authors wish to thank for financial support to Slovak Research and Development Agency APVV project No. VMSP-P-0085-09, LPP-0366-09 and APVV-0535-07.
Received 2010 06 22
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P. Spanik, M. Frivaldsky, P. Drgona, J. Kandrac Department of Mechatronics and Electronics, Faculty of Electrotechnical Engineering, University of Zilina, Univerzitna 1, 010 21 Zilina, Slovak Republic, e-mail: email@example.com
Table 1. Power losses (hard switching technique) [P.sub.ON] + [P.sub.ON] [W] [P.sub.OF] [W] [P.sub.OF] [W] IPW60R165CP 19,5 14 33,5 Table 2. Power losses (ZVS technique) [P.sub.OF] [W] [P.sub.OF] [W] [t.sub.D] 300 ns 300 ns [C.sub.OSS(AUX)] 0 nF 1 nF IPW60R165CP 7 3,8 [P.sub.OF] [W] [P.sub.OF] [W] [t.sub.D] 500 ns 500 ns [C.sub.OSS(AUX)] 0 nF 1 nF IPW60R165CP 6,7 2,7 Table 3. Power losses during turn on process (ZCS technique) [P.sub.ON] [W] [t.sub.D] 300 ns 500 ns 1 us IPW60R165CP 3,8 3,42 3,4
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|Author:||Spanik, P.; Frivaldsky, M.; Drgona, P.; Kandrac, J.|
|Publication:||Elektronika ir Elektrotechnika|
|Date:||Nov 1, 2010|
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