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ECG front end data acquisition system with CMOS technology.


Data acquisition is the process of sampling signals that quantify real world physical conditions and converting the resulting samples into digital numeric values that can be manipulated by a computer. Data acquisition systems, abbreviated by the acronyms DAS, usually convert the analog waveforms into the digital values for processing. Electrocardiogram (ECG) is a depictive recording of electrical activity of the heart over time. It is frequently recognized by the biological signal, and with non-invasive method; it is generally used for analysis of some diseases by construing the signal. Cardiovascular diseases and its abnormalities change the ECG wave shape; each portion of the ECG waveform carries information that is pertinent to the clinician in arriving at a proper diagnosis is shown in Fig.1.

The ECG sensor is to obtain the effect of the human body heart sounds ECG signal, translates into electrical signal, the signal is generally unsteady, accompanied by noise, and should be based on the modulation circuit filter and amplification. A signal acquisition still hardware and software instrumentation, noise or other distinctiveness filtering and dealing out for the evocation of information. Signal processing is performed in the vast majority of systems for ECG analysis and interpretation. It is used to extract several characteristic parameters. Presently, biomedical signal processing have been towards quantitative or the objective analysis of physiological systems and phenomena via signal analysis. The purpose of ECG signal processing is diverse and it comprises the improvement of measurement accuracy and reproducibility.

ECG analysis concerns resting ECG elucidation, stress testing, peripatetic monitoring, or intensive care monitoring, which forms a basic set of algorithms that conditions the signal with respect to different types of noise and artifacts which helps to detect heartbeats, haul out basic ECG measurements of wave amplitudes and durations, and compress the data for an resourceful storage or transmission. In all these applications, the bio-signal is first preconditioned and converted to the respective digital code. A digital signal processor then processes the digital data for monitoring or diagnosis applications. Biomedical signal acquisition systems generally consist of a low-noise amplifier (LNA) and an analog-to-digital converter (ADC) is the mostly commonly used analog devices. Normally these devices drains more amount of power and area. Digital systems play a remarkable role in today's life. They have significant applications in virtually all fields of human activity and have a global influence on the performance of society. Digital portray electronic technology that generates, stores and processes data in stipulations of two states: positive and non-positive. Positive is articulated or represented by the number 1 and the non-positive by the number 0. Thus, data transmitted or stored with digital technology is asserted as a string of 0's and 1's. Each of these state digits is invoked as a bit. In a digital system, a more rigorous representation of a signal can be obtained by using more binary digits to represent it. Although this requires additional digital circuits to process the signals, each digit is directed by the same kind of hardware, proceeding in an easily scalable system.

With the enhancement of CMOS technology, the supply voltage is being reduced, which deflates the voltage headroom for analog block of an IC [1]. The technology scaling heads to the lower power consumption and higher performance in digital circuits. The parameters such as Signal-to-Noise Ratio (SNR), dynamic range and gain of the analog design of an IC are negatively impacted. The power consumption in a signal processing system is reiteratively determined by dynamic range requirements. The dynamic range is a measure of the ratio between the largest signal that can be handled by the system without a eloquent distortion and the minimum detectable signal set by the input-referred noise. Therefore, it is covetable to find new architectures in which more digital blocks are used. However, there are other issues that should be consigned before moving close to the fully digital implementation. Two of these issues are as follows [10].

1) Detaching the DC Offset Voltage of Electrodes without Passive Elements

2) Providing a Solution for Anti-aliasing Filter.

Existing system:

Biomedical signal acquisition systems [3] usually subsist of a low-noise amplifier (LNA), a band-pass filter, an analog sample and hold, and an analog-to-digital converter (ADC) is shown in Fig.2.Typically, analog block consume more amount of power and area compared to the digital architecture. This digitally enhanced approach can helps to increase the extensibility of the system in removing the unwanted interferences. Besides, the digital calibration techniques can be used more easily.

In the existing system, with the growth of CMOS technology, supply voltage is being reduced; hence it decreases the voltage headroom for analog block of an Integrated Circuit. The block diagram of the system designed in [8] is shown in Fig.3. In this circuit, many of the functions that are normally implemented by analog blocks are performed by digital circuits. Using this digitally enhanced approach can help to amplify the flexibility of the system in removing an unwanted noise. Eliminating the interferences at the input of the system, before extensive gain is applied, which can relax the dynamic range requirements and reduced the supply voltage. This can lead to reduce the overall power consumption and area of the system. [9]

This can be achieved by using mixed signal feedback and the digital circuits. Hence, the use of digital techniques in the implementation these systems that which can helps to get a better performance and better compatibility with digital CMOS technology.

Proposed system:

A new power-efficient ECG acquisition system that uses a fully digital architecture is proposed. In the system, active electrode, DCC, Demux and counter is implemented in the 90nm CMOS technology to evaluate its performance. The supply voltage is 0.3 V, and the circuits are designed to operate in the sub- threshold region to reduce the power consumption. Each block of the system and its design challenges is discussed in the following sections.

A. Proposed System Block Diagram:

The bio-signal is generated from the active electrode is directly given to the two DCC blocks which is operated based on the counter signal is shown in the Fig.4. These blocks are in charge of generating a current that depends on the 32-bit digital number (SW0 to SW31). The ECG signal acquisition system should be capable of rejecting the dc polarization voltage of the bio-potential electrodes, appearing as a dc offset at the input.

B. Active Electrode:

Active electrode is electrodes that require no skin preparation. It is possible with preamplifier positioned very close to the skin, within electrode. High dry skin impedance can be omitted by using amplifier with very high input impedance. Another motivation in order to use active electrodes is safety. A small electrode that is placed on a specific point to produce the stimulation in the concentrated area in electrotherapy.

C. Digital to Current Converter:

In the fully digital ECG front-end architecture of Fig.5 shows two DCC blocks are used. These blocks are in charge of generating a current that depends on the 32-bit digital number (SW0 to SW31) at the output of the Demultiplexer. The DCC circuit, in which generates the gate voltages required for the reference current generator in the upper circuit. The currents produced by transistors M0p to M32p and M0n to M32n pass through transistors Mp and Mn to generate the two voltages Vinp and Vinn. These voltages are then applied to the VTCp and VTCn blocks. The DCC generates a current which is proportional to its digital input and decreases/increases the input voltage of the VTCp and VTCn, each LSB of the DCC corresponds to more or less 3 mV and this voltage is added to/subtracted from the system in every step.

To recognize the behaviour of the DCC, assume that the offset at the input increases (decreases) dominated to a rise (fall) in Vinp and Vinn. As a result, the delay of the VTCp block increases (decreases) and that the VTCn decreases (increases). As can be seen, at the beginning, the offset cancellation circuit is interim and setting the output of the DCCs and after this transition time the output signal is reliable.

D. Counter:

In this architecture the counter operation is based on D Flip-Flop which is constructed by gated SR. The D Flip Flop is by far the most important of the clocked flip-flops as it never assures that inputs S and R are equal to one at the same time. The D-type flip flop is constructed from a gated SR flip-flop with an inverter added between the S and the R inputs to allow for a single D (data) input. Then single data input is labelled D, used in place of the "set" signal, and the inverter is used to produce the complementary "reset" input thereby forge a level-sensitive D-type flip-flop from a level-sensitive RS-latch as now S = D and R = not D is shown in the Fig.6

The "SET" and "RESET" of the flip-flop using presently one input as now the two input signals are complements of each other. This complement averts the ambiguity inherent in the SR latch when both inputs are LOW, hence that state is no longer exist. Thus, the single input is called the "DATA" input. If this data input is retained HIGH the flip flop would be "SET" and when it is LOW the flip flop would change and become "RESET". However, this would be rather insignificant, the output of the flip flop would always change on every pulse applied to this data input. To avoid this additional input called the "CLOCK" or "ENABLE" is used to isolate the data input from the flip flop's latching circuitry after the desired data has been stored. The outcome is that D input condition is only copied to the output Q when the clock input is active, then it forms the basis of another sequential device called a D Flip Flop. The "D flip flop" will store the output whatever the logic level is applied to its data terminal so long as the clock input is HIGH. Once the clock input runs LOW the "set" and "reset" inputs of the flip-flop are taken at logic level "1, so it will not change the state and stored whatever data was present on its output before the clock transition acquired. In further words the output is "latched" at either logic "0" or logic "1".

F Control logic:

It is composed of TCs, AND and OR gates, and set-reset (SR) latches. To detect the offset, the control logic should compare tdp with four predefined delays (tdmax, tdmin, tdml, and tdmh). Note that in an analog front end, for detecting the offset voltage, an analog voltage comparator should be used. In our design, the offset is detected by TCs, which are implemented by D flip-flops and are more power and area efficient compared with the analog voltage comparators. The outputs of the control logic circuit are the UP and DOWN signals, which control the up/down counter in the offset cancellation block. The counter in our design is implemented by NAND gates and jk flip-flops.

Simulation results:

The combined block of DCCs consists of two architecture DCCn and DCCp architecture each of this two architecture individually have 32 number of transistor in order to cancel out the DC offset is shown in the Fig.7. Here, the input is given in the two end of active electrode and the corresponding output is get from the two DCCs which is feedback to the active electrode. The NMOS gate terminal of the two DCCs architecture is connected to the switching circuit. The switching circuit has two stages of NMOS, one is inverted and other is non inverted. These two stage common gate terminal is taken as input which is fed to the DCCs architecture and whose output is given to the counter in order to operate the control logic. The output waveform of the counter is shown in the Fig.8


In the expectation of the future dominance of digital CMOS technology, a fully digital front-end architecture for an ECG acquisition system was designed. In this system, active electrode, DCC and counter circuits were implemented. The system has low power consumption, reduced delay time and less complexity. This digital architecture is simulated in 90nm CMOS technology at 0.4 V supply voltage. The simulated power consumption is 50.55nW their corresponding delay is -1.9071e-003.In future, digital architecture can be modified to accept an offset voltage larger than [+ or -]300 mV. In order to do this, the resolution of the DCC circuit and demultiplexer should be increased to 8 bits.


[1.] Sivaranjani, R. and D. Sasikala, 2017. 'Design of ECG data acquisition system using 90nm CMOS technology. 'Asian Journal of Applied Science and Technology(AJSAT), 1: 79-84.

[2.] Sivaranjani, R. and D. Sasikala, 2016. 'Design of digital circuits for ECG data acquisition system,'International Journal of Computing and Technology, 3: 477-482.

[3.] Maryam Zare and Mohammad Maymandi, Nejad, 2015. 'A fully digital front end architecture for ECG acquisition system with 0.5 V supply,' IEEE Transaction on (VLSI) Systems, 24: 256-265.

[4.] Pieter Harpe, Gao, Rainier van Dommele, Eugenio Cantatore and Arthur H. M. van Roermund, 2015. 'A 0.20 [mm.sup.2] 3 nW Signal Acquisition IC for Miniature Sensor Nodes in 65 nm CMOS', IEEE J. Solid-State Circuits, 51(1): 240-248.

[5.] Chih-Chan, Tu. And Lin. Tsung-Hsien, 2014. 'Analog Front-End Amplifier for ECG Applications with Feed-Forward EOS Cancellation', IEEE on (VLSI-DAT), pp: 1-4.

[6.] Horng-Yuan Shih, Sheng-Kai Lin and Po-Shun Liao, 2014. 'An 80* Analog-Implemented Time-Difference Amplifier for Delay-Line-Based Coarse-Fine Time-to-Digital Converters in 0.18-pm CMOS', IEEE (VLSI) Systems, 23: 1528-153.

[7.] Hyejung Kim, Sunyoung Kim and Nick Van Helleputte, 2013. 'A Configurable and Low-Power Mixed Signal SOC for Portable ECG Monitoring Applications', IEEE Biomedical Circuits And System, 8: 257267.

[8.] Bo-Yu Shiu, Shuo-Wei Wang, Yuan-Sun Chu and Tsung-Heng Tsai, 2013. 'Low-Power Low-Noise ECG Acquisition System with DSP for Heart Disease Identification', IEEE Biomedical Circuits and System, pp: 21-24.

[9.] Rikky Muller, Simone Gambini, and M. Jan Rabaey, 2012. 'A 0.013 mm2, 5 p W, DC-Coupled Neural Signal Acquisition IC with 0.5 V Supply', IEEE J. Solid-State Circuits, 47(1): 232-243.

[10.] Tsung-Heng Tsai, Jia-Hua Hong and Shuenn-Yuh Lee, 2012. 'Low-Power Analog Integrated Circuits for Wireless ECG Acquisition Systems', IEEE Information Technology In Biomedicine, 16(5): 907-917.

[11.] Bohorquez, J.L., Yip. Marcus, A.P. Chandrakasan, J.L. Dawson, 2011. 'A biomedical sensor interface with a sinc filter and interference cancellation', IEEE J. Solid-State Circuits, 46(4): 746-756.

(1) R. Sivaranjani, (2) Dr.D. Sasikala

(1) PG student, Department of ECE, Vivekanandha College of Engineering for Women, Tiruchengode, India

(2) HEAD /ECE, Department of ECE, Vivekanandha College of Engineering of Women, Tiruchengode, India

Received 28 January 2017; Accepted 22 March 2017; Available online 28 April 2017

Address For Correspondence:

R. Sivaranjani, PG student, Department of ECE, Vivekanandha College of Engineering for Women, Tiruchengode, India


Caption: Fig. 1: ECG Waveform.

Caption: Fig. 2: Biomedical signal acquisition system.

Caption: Fig. 3: Mixed signal feedback architecture.

Caption: Fig. 4: Proposed system block diagram.

Caption: Fig. 5: Structure of the current DCC.

Caption: Fig. 6: D Flip-Flop.

Caption: Fig. 7: Schematic Diagram of control logic.

Caption: Fig. 8: Output waveform of the Control logic block.
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Author:Sivaranjani, R.; Sasikala, D.
Publication:Advances in Natural and Applied Sciences
Article Type:Report
Date:Apr 30, 2017
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