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Doubling DSP efficiency with high-performance SRAM.

With well-defined architecture and deterministic processing, DSPs accelerate the performance of a wide range of military and defense applications, including radar, software defined radio (SDRs), aircraft imaging, and target detection systems. By removing memory bottlenecks by using high-performance quad data rate (QDR) SRAM as compared to traditional SDRAM, overall DSP system can be doubled.

Applications like radar systems use DSPs to perform compute-intensive functions, such as pulse compression, signal filtration, and pulse modulation. The efficiency of DSPs enables these systems to accurately detect objects at long range. A primary difference between DSPs and general-purpose microprocessors is how DSP architectures are designed for the fast mathematical calculations most commonly used to design filters like FFTs and FIRs.

Two main hardware approaches are used for implementing DSPs: programmable DSP processors and field programmable gate arrays (FPGAs). DSP processors, like TI's multicore DSP processor, have specialized hardware to compute multiplication operations in one cycle. The instruction set of modern DSP processors allows programmers to specify several parallel operations in a single instruction. These efficient instructions often require multiple memory transactions to be made in parallel with the main arithmetic operation. Furthermore, advanced DSP architectures now include additional multipliers and adders that encode parallel operations in a single instruction.

FPGAs like Xilinx's Virtex efficiently implement algorithms using dedicated hardware-based functions, such as multiply, multiply accumulate, add, shift, compare, bit-wise logic functions, and pattern detect. More complex functions are implemented by cascading multiple blocks together.

Addressing memory throughput requirements

Because each DSP instruction can access memory multiple times, high-memory bandwidth is essential to maximizing DSP performance. DSP processors and FPGA-based DSP blocks use an internal cache memory architecture (L1/L2) to enable multiple memory accesses per cycle. A super Harvard architecture can be used when there are separate instruction and data memory banks. With this arrangement, the processor can fetch instructions and data operands in parallel, every cycle.

Because DSP-based algorithms typically access memory in a predictable pattern, throughput is dependent upon how well the memory can fit the pattern. For example, FIR filter coefficients are accessed sequentially and in a circular fashion. For deeper external storage, hardware-based external memory interfaces (EMIF) supporting various SDRAM memories (DDR2/3, RLDRAM) are typically employed. To improve DSP performance by a factor of 2, a new and innovative technique using QDR SRAM for external storage can be implemented.

QDR SRAM is a high-performance memory device optimized for high throughput. These memories have multiple independent data ports equipped with double data rate (DDR) interfaces. Port accesses are concurrent and independent of each other. The address bus is common and runs at either single or double data rate, depending upon the configuration. The highest density product available today is 144 Mbit and can be configured as either x18 or x36.

The benefit of using QDR-IV SRAM can be shown in an SAR radar application. SAR radars observe the earth's surface in high resolution. They need corner-turn memory access where the range direction and the azimuth direction are transposed for reconstruction processing. This is done for efficient FFT and IFFT (DSP) execution between range and azimuth compress processing. The architectural benefits of QDR SRAMs can improve SAR radar's performance by allowing fast and uniform memory access times.

Using a conventional SDRAM memory, writing of the SAR picture data ends up in a discontinuous address space, leading to a reduction in processor performance (in this case, estimated at roughly five times). QDR-IV's independent ports for reading and writing enable concurrent operations and random memory access, mitigating this processing penalty.

QDR SRAMs provide a beneficial performance alternative to conventional SDRAMs for off-chip data storage in DSP-based applications. QDR SRAM density limitations can be mitigated by cascading multiple devices. This approach is ideal for applications where higher throughput with random access is required to speed memory access and improve overall DSP performance.

By Suhail Zain, Director of New Product Development Strategic Marketing for Aerospace & Defense, Cypress Semiconductor Corp.
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Title Annotation:DESIGN TALK: Military
Author:Zain, Suhail
Publication:ECN-Electronic Component News
Date:Feb 1, 2015
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