Direct Current Sputter Epitaxy of Heavily Doped [p.sup.+] Layer for Monocrystalline Si Solar Cells.
Crystalline silicon is by far the most important photovoltaic technology today because of its high efficiency, abundant raw materials, well investigated materials and techniques, and abundant infrastructures for fabrication raised by semiconductor industries. For further cost reduction of monocrystalline Si solar cells (SCs), both decreasing material usage by means of thin film and increasing power generation by increasing energy conversion efficiency are two effective methods. As for the approach by means of thin films, transferring of thin epitaxially grown Si film on Si wafer to foreign substrates is a promising method [1-3]. As for the latter approach, several structures of Si SC have been proposed and realized. The world record energy conversion efficiencies of monocrystalline Si solar cell (SC) had long been 24.0% since Green et al. announced passivated emitter with rear locally diffused (PERL) structure in 1999 [4, 5]. It was not until 2014 that the record was broken, almost simultaneously by heterojunction with intrinsic thin-layer (HIT) structure with 25.6%  efficiency and interdigitated-back-contact (IBC) structure of 25.0%  efficiency. In IBC SCs, both cathode and anode electrodes for, respectively, electron and hole collection were at the rear side of the device, and there are no light shielding electrodes on front, so a short-circuit current density as high as 41.33 mA[cm.sup.-2] was achieved for the record IBC SC. In IBC SC, pitch between [n.sup.+] and [p.sup.+] region is much smaller than diffusion length of excess carriers for a better carrier collection; however, the pitch was limited by alignment between the [n.sup.+] regions and the [p.sup.+] regions. Besides, these [n.sup.+] and [p.sup.+] regions are generally formed by thermal diffusion at a temperature higher than 800[degrees]C. This process increases thermal budget, which may result in a reduced surface dopant concentration, increased diffusion depth of preformed doping region, and reduced excess carrier lifetime due to thermal degradation. Thus alternative method for formation of shallow and heavily doped [n.sup.+] and [p.sup.+] region under low thermal budget was demanded. To address this problem, we have proposed applying sputter epitaxy for [n.sup.+] emitter for SCs [8, 9]. This is a low-temperature process--so forgoing dopants did not diffuse during subsequent opposite dopant type region formation--and also is a low-pressure process, so shadow-mask patterning with a minimum line and space width of ~0.08mm can be realized . In our previous study, Sb was cosputtered with Si to grow [n.sup.+]-Si on Si substrate, and an abrupt dopant profile with a maximum Hall carrier concentration at 3 x [10.sup.2] [cm.sup.-3] was obtained . Furthermore, [n.sup.+] emitter was grown on p-Si to form [n.sup.+]p SCs and had demonstrated that internal quantum efficiency (IQE) of the SCs around visible light can be as high as 95%, even higher than that in SCs with conventional thermal diffusion emitter . Compared to [n.sup.+]-Si region, formation of [p.sup.+]-Si region is still a research challenge for [p.sup.+] emitter in emerging [p.sup.+][nn.sup.+] Si SCs . Heavy and shallow [p.sup.+] layer is demanded for reducing Auger recombination. However, low diffusion coefficient and solubility of boron lead to a higher diffusion temperature and lower peak carrier concentration. By means of low-temperature sputter epitaxy, it is possible to form [p.sup.+] layer with sufficient carrier concentration. In this study, heavily doped [p.sup.+] was sputter epitaxially grown on n-Si wafer to fabricate [p.sup.+][nn.sup.+] SCs for the first time, and the characteristics of the [p.sup.+]n SCs were demonstrated.
2. Experimental Methods
3-inch magnetron Ar (99.9999%) direct current (DC) sputter with ultimate pressure of 6 x x [10.sup.-5] Pa was used for sputter epitaxy. For sputter epitaxy of [p.sup.+]-Si film, 2 rice-grainsized boron lumps (99.8%) adhered to nondoped Si wafer through pure gallium solder were used as a target. The positions of boron lumps are at erosion region of the target. For sputter epitaxy of [n.sup.+]-Si film, an Sb chip (99.999%) with total area of 1.5 [cm.sup.2] was placed on the Si target as a source of donor impurities. Ar flow rate was 3-5sccm which raised chamber pressure to 5.5 x [10.sup.-1] Pa. The cathode power was kept at 100 W over this study. Details on sputter epitaxy can be further referred to in our previous studies [8, 9]. [p.sup.+]n monocrystalline Si SCs were fabricated, together with [n.sup.+]p monocrystalline Si SCs for comparison. Schematic fabrication process and cross-sectional structure of [p.sup.+]n SCs or [p.sup.+][nn.sup.+] SCs were shown in Figure 1(a) and cross-sectional structure of [n.sup.+]p SCs was shown in Figure 1(b). For [p.sup.+]n SCs, 0.325 mm thick two-side mirror polished n-type Si(100) wafer with a resistivity of 1-10 [OMEGA] x cm was used as substrate. The substrate was first cleaned with ozonated deionized (DI) water for 30 min, then treated in 1% HF solution, rinsed in DI water, and then loaded into sputter chamber. [p.sup.+] emitter with a thickness among 10 nm to 200 nm was epitaxially grown on the substrate at 315[degrees] C. The total area of SC was 10 x 10 [mm.sup.2]. In a part of [p.sup.+]n SCs, [n.sup.+]-Si film for back surface field (BSF) as well as ohmic contact with back Ag electrode was grown on the back surface of Si wafer, with a thickness [d.sub.BSF] among 10 to 1000 nm. A part of samples was annealed by rapid thermal annealing (RTA) for 5 min at temperature [T.sub.anneal] in vacuum. Finally, the front Al finger electrodes and whole rear surface Ag electrode were deposited by DC sputtering at room temperature. The side edges of the SCs were slightly polished with a sanding paper to remove the side [p.sup.+] or [n.sup.+] layer. For [n.sup.+]p SCs, the conduction type of both substrate and emitter layer and surface and rear metal were totally reversed from [p.sup.+]n SCs. The Hall carrier concentration of [p.sup.+] and [n.sup.+] layer for emitters was 1-3 x [mm.sup.20] [cm.sup.-3]. The current density and voltage (J-V) relationship with and without the AM1.5G solar simulator illumination and the internal quantum efficiency (IQE) were measured (Oriel Instruments IQE200).
3. Results and Discussion
Figures 2(a)-2(c) show the reflection high energy electron diffraction (RHEED) patterns of the Si surface after growth of, respectively, 100 nm, 500 nm, and 1000 nm SE-Si film on Si(100), at the  azimuthal angle. Diffraction spots from the (001) surface were clearly observed in these deposited films, indicating that the films were grown epitaxially on Si(100). These patterns do not look too much different from one another, indicating the crystal quality did not degrade much increasing epitaxial thickness. Hall hole concentration p, mobility and resistivity [rho], of as-deposited [p.sup.+] epitaxial film were, respectively, 2.6 x [mm.sup.20] [cm.sup.-3], 5 [cm.sup.2] [V.sup.-1][s.sup.-1], and 4.9 x [10.sup.-3] [OMEGA]cm. p was larger than the solubility of B (~1 x [10.sup.20] [cm.sup.-3]) at 900[degrees]C, attributed to the nonequilibrium doping in sputter epitaxy. This result shows applicability of sputter epitaxy for forming shallow and heavy doped [p.sup.+] layer. It is worth noting that we have also tried to use Al or Ga for inducing acceptor dopant; however, carrier concentrations of grown film were all under [10.sup.17] [cm.sup.-3], and further increasing of dopants always resulted in obstacle of epitaxy.
Figure 3(a) shows logarithmic photo and dark J-V characteristics of [n.sup.+]p SC and [p.sup.+]n SC without BSF layer ([d.sub.BSF] = 0), and Figure 3(b) shows linear photo J-V characteristics of these SCs. Here the photocurrent was measured under AM1.5 light illumination. The samples were not annealed after [p.sup.+]nor [n.sup.+]p junction formation. Clear rectifying characteristic with an on/off ratio exceeding 3 orders was observed in [n.sup.+]p SCbut not observed in [p.sup.+]n SC. Furthermore J-V characteristics of [p.sup.+]n SC in Figure 3(b) flattened at 0.4 V, suggesting existence of shottky barrier between n-Si base and Ag rear electrode. J-V characteristics of [p.sup.+][nn.sup.+] SC with [d.sub.BSF] = 50 nm were shown in Figures 3(a) and 3(b). The device exhibited a clear rectifying characteristic by inserting rear [n.sup.+] layer. Still, short-circuit current density [J.sub.sc] and open circuit voltage [V.sub.oc] of, respectively, 17.0 mA/[cm.sup.2] and 0.373 V were still much worse than those of [n.sup.+]p SCs of 22.6 mA/[cm.sup.2] and 0.510 V. Internal quantum efficiency, IQE, and reflectivity, R, of both [n.sup.+]p and [p.sup.+][nn.sup.+] SCs are shown in Figure 4. The reflectivity of SCs was the same among all SCs fabricated in this study, which was almost the same as that of mirror polished Si wafer. At ultraviolet light (wavelength [lambda] < 400 nm), IQE of [p.sup.+][nn.sup.+] SC was 17-25% and was higher than that of [n.sup.+]p SC of 5-10%. This suggests a little light absorption in [p.sup.+] compared with that in [n.sup.+]. Thus a better conversion efficiency can be expected by using [p.sup.+] emitter compared to [n.sup.+] emitter in conventional BSF structure solar cells. However at visible light (400 nm < [lambda] < 1000 nm), IQE of [p.sup.+][nn.sup.+] SC was around 80% and is much smaller than that of [n.sup.+]p SC at around 95%. Defects were induced in base during emitter formation, and the degree is worse for [p.sup.+]-emitter than for [n.sup.+]-emitter. Annealing is effective at reducing defects. Figure 5(a) shows J-V characteristics of [p.sup.+][nn.sup.+] SC before and after annealing at 400[degrees]C, 600[degrees]C, and 800[degrees]C. At 800[degrees]C, [J.sub.sc] improved from 17.0 to 22.1mA/[cm.sup.2] and [V.sub.oc] correspondingly improved from 0.373 V to 0.473 V. Figure 5(b) shows IQE and R of these SCs. IQE improved drastically over all wavelength at 800[degrees]C. The IQE improved among ultraviolet (UV) light suggested defects in [p.sup.+]-emitter have been declined, and that among visible light suggested defects in n-base have been declined. A shoulder appeared at near infrared (NIR) (1000 nm < [lambda] < 1200 nm) at samples with [T.sub.anneal] > 400[degrees]C, meaning carrier correction at vicinity of rear surface increased in absence of [n.sup.+] layer with annealing. Therefore, the rear [n.sup.+] layer not only behave as ohmic contact layer but also behave as a BSF layer. Figure 6 shows IQE and R of [p.sup.+][nn.sup.+] SCs with [n.sup.+] BSF thickness [d.sub.BSF] varied among 10 nm to 1000 nm. [T.sub.anneal] was kept 800[degrees]C, and [d.sub.emit] was kept 100 nm in all samples. The shoulder at NIR presented even when [d.sub.emit] = 10 nm, decreased with increasing [d.sub.emit], and almost disappeared at [d.sub.emit] = 1000 nm. From the above results, functions of rear [n.sup.+] layer can be induced as follows. After rear [n.sup.+] layer growth, defective layer was induced in base substrate at vicinity of rear surface. In this condition, although rear [n.sup.+] layer still works as ohmic contact layer between n-base and Ag electrode, collecting yield of photo carriers excited by NIR near rear surface is low because of active carrier recombination in the defective layer at base rear surface. [n.sup.+] BSF layer is ineffective since there are few excess minority carriers in the defective layer. After the sample was annealed, defective layer recovered, and collecting yield of excess carriers at rear surface increased. When [d.sub.BSF] was increased, unnecessary absorption of NIR takes place in the BSF layer as a dead layer, so IQE decreased.
Figures 7(a) and 7(b), respectively, show J-V and IQE characteristics of [p.sup.+][nn.sup.+] SCs with [d.sub.emit] among 10 nm to 200 nm. Based on Figure 7(a), [J.sub.sc], [V.sub.oc], series resistance Rs, shunt resistance [R.sub.sh], conversion efficiency [eta], and fill factor ff were extracted and were shown in Figure 8 as functions of [d.sub.emit]. Here, the value of RSH was calculated from -dV/dJ at V = 0, and the value of [R.sub.S] was calculated from -dV/dJ at J = 0. With decreasing [d.sub.emit] to 10 nm from 100 nm, [R.sub.sh] decreased from 100 Qcm to 50 Qcm because of increased short possibility between top electrode and n-base through pin-holes in [p.sup.+]-Si emitter. Accordingly ff decreased, which resulted in [J.sub.sc] and [V.sub.oc] decrement. On the other hand, with increasing [d.sub.emit] from 100 nm to 200 nm, [J.sub.sc] decreased from 22.8mA/[cm.sup.2] to around 20mA/[cm.sup.2] with keeping [R.sub.sh] and FF almost constant. This is because of unnecessary light absorption in the emitter layer, as was shown in Figure 7(b) where IQE decreased drastically at [lambda] < 400 nm. The optimum [d.sub.emit] for [p.sup.+][nn.sup.+] SCs were therefore at 100 nm. In the optimum condition, [eta] of [p.sup.+][nn.sup.+] SCs exhibited 5.77%, which is comparable to that of [n.sup.+]p SCs at 5.43%. [eta] of SCs was low compared to typical monocrystalline Si SCs. This is because techniques for increasing light absorption and for passivating defects were not applied in this study. Still, SCs with thin [p.sup.+] emitter and with thin [n.sup.+] BSF demonstrated an excellent IQE, suggesting a potential of sputter epitaxy for application to Si solar cells.
[p.sup.+] emitter layer and [n.sup.+] BSF layer were sputter epitaxially grown on n-type Si for fabricating [p.sup.+][nn.sup.+] SCs, and influences of these films on solar-cell characteristics were investigated. Hall carrier concentration of [p.sup.+] emitter layer was as high as 2.6 x [mm.sup.20] [cm.sup.-3] owing to cosputtering of B with Si at low temperature, which had enabled heavy and shallow [p.sup.+] layer. IQE of [p.sup.+][nn.sup.+] SCs at visible light was larger than 95%; even at UV light it was larger than 50% for an emitter thinner than 50 nm. At NIR, extra increment on IQE was achieved by rear [n.sup.+] BSF layer with a thickness thinner than 100 nm. This method provides a new method for fabricating pn junction based Si solar cells.
Conflicts of Interest
The authors declare that they have no conflicts of interest.
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Wenchang Yeh and Hikaru Moriyama
Interdisciplinary Graduate School of Science and Engineering, Shimane University, Nishikawatsu-cho 1060, Matsue 690- 8504, Japan
Correspondence should be addressed to Wenchang Yeh; email@example.com
Received 21 September 2016; Accepted 15 March 2017; Published 7 May 2017
Academic Editor: Sundaram Senthilarasu
Caption: Figure 1: (a) Schematic fabrication process and cross-sectional structure of [p.sup.+]n SCs or [p.sup.+][nn.sup.+] SCs. (b) Cross-sectional structure of [n.sup.+]p SCs.
Caption: Figure 2: RHEED patterns of the Si surface after growth of, respectively, (a) 100 nm, (b) 500 nm, and (c) 1000 nm Si film on Si(100), at the  azimuthal angle.
Caption: Figure 3: (a) Logarithmic photo and dark J-V characteristics of [n.sup.+]pSC and [p.sup.+]n SC without BSF layer and (b) linear photo J-V characteristics of the SCs. The photocurrent was measured under AM1.5 light illumination. The samples were not annealed after [p.sup.+]n or [n.sup.+]p junction formation.
Caption: Figure 4: IQE and R of both [n.sup.+]p SCs and [p.sup.+][nn.sup.+] SCs.
Caption: Figure 5: (a) J-V characteristics of [p.sup.+][nn.sup.+] SCs before and after annealing at 400[degrees]C, 600[degrees] C, and 800[degrees]C. (b) IQE and R of these SCs.
Caption: Figure 6: IQE and R of [p.sup.+][nn.sup.+] SCs with [n.sup.+] BSF thickness [d.sub.BSF] varied among 10 nm to 1000 nm.
Caption: Figure 7: (a) J-V characteristics and (b) IQE characteristics of [p.sup.+][nn.sup.+] SCs with [d.sub.emit] among 10 nm to 200 nm.
Caption: Figure 8: [J.sub.sc], [V.sub.oc], [R.sub.s], [R.sub.sh], [eta], and ff of [p.sup.+][nn.sup.+] SCs as functions of [d.sub.emit].
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|Title Annotation:||Research Article|
|Author:||Yeh, Wenchang; Moriyama, Hikaru|
|Publication:||Journal of Solar Energy|
|Date:||Jan 1, 2017|
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