# Digital filter design: learn more about the role of DSP in digital filters for today's applications.

Digital signal processors (DSPs) continue to receive a great deal of attention in new product design. For example, digital filter design reflects the importance of understanding and using this technology to provide precision, stand-alone digital or integrated analog/digital product solutions.By using DSPs capable of sequencing and reproducing hundreds to thousands of discrete elements, design models can be used to simulate large hardware structures at relatively low cost. DSP techniques perform functions such as fast Fourier transforms (FFT), delay equalization, programmable gain, modulation, encoding/decoding, and filtering.

[FIGURE 1 OMITTED]

Programs can be written where:

* Filter weighting functions (coefficients) can be calculated on the fly to reduce memory requirements.

* Algorithms can be dynamically modified as a function of signal input.

DSP represents a subset of signalprocessing activities that use analogto-digital converters (ADCs) to turn analog signals into streams of digital data. A stand-alone digital filter requires an ADC with an associated antialias filter, a DSP chip, and a PROM or software driver.

An extensive sequence of multiplications and additions then can be performed on the digital data. In some applications, the designer also may want to place a digital-to-analog converter (DAC), accompanied by a reconstruction filter, on the output of the DSP to create an analog equivalent signal. Figure 1 shows a typical digital filter configuration.

Digital filters process digitized or sampled signals. They perform an extended sequence of multiplications and additions carried out at a uniformly spaced sample interval. These signals are passed through structures that shift the clocked data into adders, delay blocks, and multipliers. These structures change the mathematical values in a predetermined way. The resulting data represents the filtered or transformed signal.

Distortion and noise can be introduced into digital filters simply by the conversion of analog signals into digital data, the digital filtering process itself, and conversion of processed data back into analog. When fixed-point processing is used, additional noise and distortion may be added during the filtering process because the filter consists of large numbers of multiplications and additions that produce errors, creating truncation noise. Increasing the bit resolution beyond 16 b reduces this filter noise.

For most applications, as long as the ADCs and the DACs have high enough bit resolution, distortions introduced by the conversions are less of a problem. Theoretically, the ratio of the rms value of a full-scale sine wave to the rms value of the quantization noise expressed in decibels is

SNR = 6.02N + 1.76 dB

Where: N = the number of bits in the ideal ADC

Although DSPs rarely serve exclusively as anti-alias filters, they can offer features that have no practical counterpart in the analog world. Some examples are a linear phase filter that provides steep rolloff characteristics or a programmable digital filter that allows the signal conditioning to be changed on the fly via software. Frequency response or filter shape can be altered by loading stored or calculated coefficients into a DSP program.

Instead of using a commercial DSP with software algorithms, a digital hardware filter also can be constructed from logic elements such as registers and gates or an integrated hardware block such as a field programmable gate array (FPGA). Digital hardware filters are desirable for high bandwidth applications, but the tradeoffs are limited design flexibility and higher cost.

Fixed-Point DSP and FIR Implementations

Fixed-point DSP processors account for most DSP applications because of their smaller size and lower cost. The fixed-point math requires programmers to pay significant attention to the number of coefficients used in each algorithm when multiplying and accumulating digital data to prevent distortion caused by register overflow and a decrease of the signal-to-noise ratio caused by truncation noise. The structure of these algorithms uses a repetitive delay-and-add format that is represented in Figure 2.

Finite impulse response (FIR) filters are implemented using a finite number of delay taps (n) on a delay line and n computation coefficients to compute the filter function. The structure is nonrecursive, a repetitive delay-and-add format, and most often used to produce FIR filters. It depends upon each sample of new and present value data.

FIR filters create transfer functions that have no equivalent in linear circuit technology. They offer shape-factor accuracy and stability equivalent to very high-order linear active filters that cannot be achieved in the analog domain. Unlike infinite impulse response (IIR) filters, FIR filters are formed with only the equivalent of zeros in the linear domain. This means that the taps depress or push down the amplitude of the transfer function. The amount of depression for each tap depends on the value of the multiplier coefficient. For this reason, the total number of taps determines the steepness of the slope. This can be inferred from the structure shown in Figure 2.

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The number of taps and the values of the computation coefficients ([h.sub.0], [h.sub.1],..[h.sub.n]..) are selected to weight the data being shifted down the delay line to create the desired amplitude response of the filter. In this configuration, there are no feedback paths to cause instability.

The calculation coefficients are not constrained to particular values and can be used to implement filter functions that do not have a linear system equivalent. More taps increase the steepness of the filter rolloff while increasing calculation time and, for highorder filters, limiting bandwidth.

The filter delay is calculated for the structure as:

Delay = (1/2 x taps)/sampling rate For example, a 300-tap filter with a sampling rate of 48 kHz yields a minimum 3.125-ms delay.

Designers also must be aware of the trade-offs between phase delay and filter precision when designing FIR filters. The bad news is that high-order FIR filters have longer delay. The good news is that the phase response remains linear as a function of frequency. In applications where linear phase is critical and long phase delay cannot be tolerated, a linear active Bessel or a constant delay filter may be a better selection.

Design Techniques for Digital FIR Filters

Two very different design techniques are commonly used for digital FIR filters: windows and equiripple.

Windows

The simplest technique used to develop digital FIR filters is windowed filters. This technique is based on designing a filter using well-known frequency-domain transition functions called windows. The use of windows often involves choosing the lesser of two evils.

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Some windows, such as the rectangular, yield fast rolloff in the frequency domain but have limited attenuation in the stop band along with poor group delay characteristics. Other windows, like the Blackman, have better stopband attenuation and group delay but a wide transition band, the bandwidth between the corner frequency and the frequency attenuation floor.

Windowed filters are easy to use and scalable and can be computed on the fly by the DSP. This latter point means that a tunable filter can be designed with the only limitation on corner frequency resolution being the number of bits in the tuning word.

Equiripple

An equiripple or Remez Exchange design technique provides an alternative to windowing by allowing the designer to achieve the desired frequency response with the fewest number of coefficients. This is accomplished by an iterative process of comparing a selected coefficient set to the actual frequency response specified until the solution is obtained that requires the fewest number of coefficients.

Though the efficiency of this technique obviously is very desirable, there are some concerns:

* For equiripple algorithms, some values may converge to a false result or not converge at all. For that reason, all coefficient sets must be pretested offline for every corner frequency value.

* Application-specific solutions that require signal tracking or dynamically changing performance parameters typically are better suited for windowing since convergence is not a concern with windowing.

* Equiripple designs are based on the optimization theory and require an enormous amount of computation effort. With the availability of today's desktop computers, the computational intensity requirement is not a problem. But combined with the possibility of convergence failure, equiripple filters typically cannot be designed on the fly within the DSP.

Many people will use windowing such as a Kaiser window to produce good, scalable FIR filters fairly quickly without the worry of nonconvergence. However, if you are interested in producing the highest-performance digital filter for a given hardware configuration the iterative Remez Exchange algorithm is worth the test.

Figure 3 illustrates a major advantage that a digital lowpass equiripple FIR filter can offer designers when solving signal-conditioning problems. FC1and FS1 are the corner and stop-band frequencies, respectively. The typical number of filter taps used for this - 100-dB attenuation example is around 300.

The ratio of FS1 to FC1 is 1.1, an unheard-of shape factor in the analog world. To achieve a similar slope, an analog filter would have to be a 30th order filter to achieve this performance. Analog filters beyond 10 poles are very difficult to realize and tend to be noisy.

[FIGURE 4 OMITTED]

Floating-Point DSP and IIR Implementations

Like its name, a floating-point DSP can perform floating-point math, which greatly decreases truncation noise problems and allows more complicated filter structures such as the inclusion of both poles and zeros. This permits the approximation of many waveforms or transfer functions that can be expressed as an infinite recursive series.

These implementations are referred to as infinite impulse response (IIR) filters. The functions are infinite recursive because they use previously calculated values in future calculations akin to feedback in hardware systems.

The equivalent of classical linear-system transfer functions can be implemented by using IIR implementation techniques. A common procedure starts with the classic analog filter transfer function, such as a Butterworth, and applies the required transform to convert the filter equations from the complex S-domain to the complex Z-domain. The resulting coefficients yield a Z-domain transfer function in a feedback configuration with a number n of delay nodes equal to the order of the S-domain transfer function.

These implementations are referred to as IIR filters because, when a short impulse is put through the filter, the output value does not converge quickly to zero but theoretically continues decreasing over an infinite number of samples. Floating-point DSPs can produce near-equivalent analog filter transforms because they essentially use the same mathematical structure as their analog counterparts. For the same reason, they exhibit the same or worse nonlinear phase characteristics as their analog counterparts since the equivalent of poles and zeros in linear systems is reproduced with an IIR digital filter.

Figure 4 illustrates a biquad digital filter structure that computes the response of a second-order IIR transfer function. It has two delay nodes, and the computation coefficients are [A.sub.1k], [A.sub.2k], [B.sub.1k], and [B.sub.2k].

Floating-point processors do have some advantages over fixed-point processors:

* Specific DSP applications such as IIR filters are easier to implement with floating-point processors.

* Floating-point application code can have lower development costs and shorter time to market with respect to corresponding programs in a fixedpoint format.

* Floating-point representation of data has a smaller amount of probable error and noise.

After all is said, these powerful floating-point devices can emulate fixed-point processors but at higher hardware cost.

Summary

Complex digital filter functions involve millions of mathematical operations. The speed of these operations depends on a variety of factors: DSP chip speed, the number of taps, and the number of bits of accuracy in each computation.

[FIGURE 5 OMITTED]

For example, a DSP chip with a 10-MHz clock rate can serve as a simple FIR filter with 16-b precision and a corner frequency as high as 100 kHz. That same circuit can attain 24-b precision with corner frequencies up to 10 kHz.

Today, many DSP turnkey and application-specific platforms are available along with development systems for the savvy engineer who wishes to do his or her own design. Many computer programs also exist that can determine the number of taps and the values of computation coefficients required to implement a specific digital-filter performance function.

In some cases, these programs output files directly to a PROM burner or flash memory, automatically loading algorithms into the actual DSP circuit. One such software program is MATLAB[R] by The Math Works, which calculates coefficients for designated FIR filters and produces IIR filter programs.

Many hardware and software design options and trade-offs are available for providing signal-processing solutions. For that reason, having the availability of analog and DSP design and programming expertise along with application-specific intellectual property (IP) from one source can provide a strong argument for the busy design engineer to seek a turnkey or custom solution. Examples include:

* Multirate FIR filters, which can significantly extend low-frequency bandwidth limits and shorten filter delay. Both are design limitations of single rate-sampled DSP filter algorithms.

* Ultra low noise and distortion antialias and reconstruction digital filters to 120 dB.

* Low distortion signal generators to 20 b.

* ADCs and DACs with - 100 dB or better noise floors.

As DSP sample rates continue to increase, the bandwidth and performance of DSP solutions also will grow.

Digital filters primarily are used when transfer-function requirements have no counterpart in the analog world or when a DSP already resides on the circuit board to perform other functions. Digital-filter selection is the choice or trade-off between floating-point DSP IIR filters and fixed-point DSP FIR filters, which are illustrated in Figure 5.

Whether you decide on a fixed-point FIR or floating-point IIR solution, the world still is analog. In many applications, the conversion from analog to digital and back to analog is a requirement, often with limitations in bandwidth and design flexibility.

One example is range limitation, which is the maximum bandwidth imposed by the sampling rate when altering the digital filter frequency. The solution is to adjust the clock, which forces adjustments in the anti-alias and reconstruction filter, requiring multiple fixed-frequency or programmable filters that typically are not cost-effective.

Another approach adjusts the clock within the DSP by decimation or interpolation so the filter shape can be modified within the filter algorithm. This is called multirate filtering, and several decimations can be implemented in series to reach very low frequencies.

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References

1. Ingle, V.K. and Proakis, J.G., Digital Signal Processing Using MATLAB, Brooks Cole, July 11, 1999.

2. Proakis, J.G. and Manolakis, D.G., Digital Signal Processing: Principles, Algorithms and Applications, Prentice Hall; 3rd edition, Oct. 5, 1995.

3. Oppenheim, A.V., Schafer, R.W., and Buck, J.R., Discrete-Time Signal Processing, Prentice Hall; 2nd edition, Feb. 15, 1999.

by Paul R. Moffitt, Frequency Devices

About the Author

Paul R. Moffitt, director of engineering at Frequency Devices, has more than 20 years of experience in analog and digital circuit design. His education includes a B.S.E.E., an M.S.E.E., and a Ph.D. in E.E. from the University of Arkansas. Frequency Devices, 25 Locust St., Haverhill, MA, 01830, 978-374-0761, e-mail: tech@freqdev.com

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Title Annotation: | Data Acquisition |
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Author: | Moffitt, Paul R. |

Publication: | EE-Evaluation Engineering |

Date: | Nov 1, 2003 |

Words: | 2491 |

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