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Differential second-order voltage-mode all-pass filter using current conveyors.

I. INTRODUCTION

The frequency filters can be found in any electronic device and hence can be considered as the most frequently used function blocks while processing analogue signals. Although various types and topologies of frequency filters can be found in the open literature, still significant attention is paid to their design, where the new solutions follow different requirements, such as universality, multifunction, controllability, active element type, low power consumption, low supply voltage, high common mode rejection, etc. [1].

From the requirements listed above, mainly the type of the active element is considered, since based on the active element type chosen to implement the required circuit, the low power consumption and/or low supply voltage of the final function block can be also achieved [2], [3]. Besides the design of function blocks using advanced types of active elements, the design of differential filters gains an increased attention as such circuits feature the advantage of immunity from common mode noise signals, enhanced dynamic range, lower harmonic distortion, and reduce the effect of coupling between various blocks once compared to basic single-ended solutions [4], [5]. However, once describing the performance of any differential function block, only the input and output signals are assumed to be differential and from the mathematical point of view the inner structure of the function block is hidden. Therefore, the proposed circuits can be referred to as true- (or fully-) and pseudo-differential function blocks if the inner structure of the function block is also differential or rather remains single-ended, respectively. The true-differential function blocks generally feature very high common-mode rejection ratio, but the complexity of the circuit topology significantly increases [4]-[8]. On the other hand, the pseudo-differential structures are less complex from the viewpoint of their implementation and are still capable to ensure sufficiently high common-mode rejection ratio [9]-[13]. In practice, combined with true-differential circuits, the pseudo-differential function blocks can be used as last section(s) of front-end analogue signal processing path, where very high common-mode rejection ratio is no more required.

From various types of filters, the all-pass filters are widely used in analogue signal processing in order to transmit signals at frequencies equally well and change only the phase [14]. Based on that all-pass filters are used to correct the phase shift caused by analogue filtering operations without changing the amplitude of the applied signal or to delay on purpose the signal being processed. However, once designing pseudo-differential all-pass filters, the authors pay attention mainly to first-order solutions only [9]-[11]. In [12] a pseudo-differential second-order current-mode universal filter using seven active (Current Differencing Current Conveyors) and ten passive elements is presented, where only high-, low- and band-pass responses can be directly obtained. Another multifunction second-order pseudo-differential filter using three differential difference current conveyors (DDCC) and seven passive elements has been presented in [13]. This solution also offers only high-, low- and band-pass responses, and therefore, to obtain a band-stop or all-pass response additional circuitry is required. To the best knowledge of the authors, the only solution of pseudo-differential second-order all-pass filter has been presented in [15]. Although only single DVCC (Differential Voltage Current Conveyor) is employed in this solution, three resistors and three capacitors, only one being grounded, are required. Furthermore, to obtain proper frequency response two matching conditions must be fulfilled, which is also a disadvantageous feature of the circuit from [15].

In this paper, using current conveyors as active elements, we focus on the design of the pseudo-differential second-order all-pass filter working in the voltage mode. The proposed structure uses three active elements and five passive elements, all being grounded. The advantageous features of the filter are high input impedance, no matching conditions, high common-mode rejection ration and the adjustability of the quality factor via single resistor without disturbing the pole-frequency of the filter.

II. THE DDCC AND CCII DESCRIPTION

The differential difference current conveyor (DDCC), whose electrical symbol is shown in Fig. 1(a), is a six-terminal network with one low-impedance current input X, three high-impedance voltage inputs Y1, Y2, Y3, and two high-impedance current outputs Z1, Z2. For ideal active element the relationship between the terminal currents and voltages is described as follows [2]:

[v.sub.X] = [v.sub.Y1]--[v.sub.Y2] + [v.sub.Y3], (1)

[i.sub.Y1] = [i.sub.Y2] = [i.sub.Y3] = 0 (2)

[iZ1.sub. = [i.sub.X], [i.sub.Z2] =-[i.sub.X]. (3)

The second-generation current conveyor (CCII) is generally a four-terminal network as shown in Fig. 1(b). Compared to DDCC, the CCII features only single high-impedance voltage input terminal Y and the relation between the terminal currents and voltages for ideal CCII is given as [2]:

[v.sub.X] = [v.sub.Y], (4)

[i.sub.Y] = 0, (5)

[i.sub.Z1] = [i.sub.X], iZ2 = -[i.sub.X]. (6)

Taking into consideration the non-idealities of the active elements, the relations between terminal voltages and currents of DDCC can be expressed as:

[v.sub.X] = [[beta].sub.1][v.sub.Y1]--[[beta].sub.2][v.sub.Y2] + [[beta].sub.3][v.sub.Y3], (7)

[i.sub.Z1] = [[alpha].sub.1][i.sub.X], [i.sub.Z2] = ][[alpha].sub.2][i.sub.X], (8)

where [[beta].sub.j] = 1--[[epsilon].sub.vf] and [[alpha].sub.k] = 1--[[epsilon].sub.ik] (for j = {1, 2, 3} and k = {1, 2}) are the voltage and current gains of the DDCC, whereas |[[epsilon].sub.vj]| << 1 and |[[epsilon].sub.ik]| << 1 denote the voltage and current tracking errors, respectively. Similarly, the non-ideal behaviour of the CCII can be defined as follows:

[v.sub.X] = [[delta][v.sub.Y], (9)

[i.sub.Z1] = [[gamma].sub.1][i.sub.X], [i.sub.Z2] = -[[[gamma].sub.2][i.sub.X] (10)

where [delta] = 1--[[epsilon].sub.v] and [[gamma].sub.k] = 1--[[epsilon].sub.k] (for k = {1, 2}) are the voltage and current gains of the DDCC, whereas |[[epsilon].sub.v]| << 1 and |[[epsilon].sub.ik]| << 1 represent the voltage and current tracking errors, respectively. Note that the currents flowing into the input voltage Y terminals of the active elements are assumed to be zero due to in practice high input impedance of these terminals.

III. PROPOSED ALL-PASS FILTER

For sake of description and analysis of the proposed pseudo-differential all-pass filter, the following notation is assumed [14]

[v.sub.id] = [v.sub.i1]--[v.sub.i], [v.sub.ic] = [v.sub.i1] + [v.sub.i2]/2, [v.sub.0d] = [v.sub.o1]--[v.sub.o2] (11)

where [v.sub.id], [v.sub.id] and [v.sub.od] denote differential-mode input, common-mode input and differential-output voltage, respectively. The differential input signal [v.sub.id] is simply the difference between the two input signals [v.sub.i1] and [v.sub.2], whereas the common-mode input signal v.c is the average of the two input signals. The differential-output voltage [v.sub.od] is then represented as

[v.sub.od] = [A.sub.dm][v.sub.id] + [A.sub.cm][v.sub.id], (12)

where [A.sub.dm] and [A.sub.cm] are the differential and common-mode gains, respectively. To evaluate the rejection of common-mode signals in preference to differential signals, common-mode rejection ratio (CMRR) is used

CMRR = 20log |[A.sub.dm]/[A.sub.cm]| (13)

The proposed pseudo-differential frequency filter is shown in Fig. 2. Assuming ideal active elements defined by (1)-(6), the output voltages [v.sub.o1] and [v.sub.o2] can be expressed as follows:

[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] (14)

[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] (15)

According to (11), for differential output voltage [v.sub.od] it holds

[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] (16)

Comparing (15) to (12), the differential gain [A.sub.dm] of the proposed pseudo-differential filter is

[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] (17)

whereas the common-mode gain [A.sub.cm] is zero, and therefore the common-mode rejection ratio (8) is infinitely high.

From (12) it can be seen that a second-order all-pass filter is obtained from the proposed filter without any matching conditions. The angular pole-frequency and quality factor Q of the filter are given as:

[[omega].sub.0] = [square root of (1/[C.sub.1][C.sub.2][R.sub.1][R.sub.2])], (18)

Q = [R.sub.3][square root of ([C.sub.1]/[C.sub.2][R.sub.1][R.sub.2])], (19)

while the pass-band voltage gain in the whole frequency range is unity. From (13) it can be seen that the quality factor Q of the filter can be adjusted independently of the angular pole-frequency [[omega].sub.0] changing the value of the resistor R3, similarly as in [16], and in case of pseudo-differential all-pass filters has not been presented so far. To offer such feature, the use of five passive elements is obligatory. The use of DDCC1 is also obligatory to obtain a differential input, similarly as e.g. in [13]. Furthermore, since the input signal is directly applied to the Y terminals of DDCC1, the circuit features high input impedance, which is advantageous once connecting the circuit in cascade to other voltage-mode function blocks. Also, no capacitors are connected to the low-impedance terminals X of the active elements and hence, as shown later, no additional parasitic poles are created in the transfer function once non-ideal active elements are assumed. Note that the DDC[C.sub.2] can be generally replaced by an inverting second generation current conveyor (ICCII) [17] and hence more simple solution can be presented. However, for sake of further analysis described below, we assume the solution as shown in Fig. 2.

Taking into consideration the non-idealities of the active elements as described by (7)-(10), the reanalysis of the proposed filter yields the following differential and common-mode gains:

[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] (20)

[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] (21)

where for sake of simplicity the non-ideal parameters of DDC[C.sub.1] and DDC[C.sub.2] were assumed to be equal.

According to (13), the common-mode rejection ratio of the filter using non-ideal active elements is

CMRR = 20log |[[beta].sub.1] + [[beta].sub.2]/2([[beta].sub.1]--[[beta].sub.2], (22)

and hence to ensure high rejection of common-mode voltage at the output, the voltage tracking errors evj must be of such values to maintain [[beta].sub.1] [approximately equal to] [beta].sub.2].

Due to the non-ideal voltage and current gains of the active elements, the angular pole-frequency and quality factor Q are affected:

[[omega].sub.0] = [square root of ([[alpha].sub.1][[beta].sub.2] [[gamma].sub.1][delta]/[C.sub.1][C.sub.2][R.sub.1][R.sub.2])], (23)

q = [R.sub.3]/[[alpha].sub.3][[beta].sub.3]= [square root of ([[alpha].sub.1][[beta].sub.2] [[gamma].sub.1][delta][C.sub.1]/[C.sub.2][R.sub.1][R.sub.2])], (24)

however, it is obvious that the feature of adjusting Q independently of [[omega].sub.0]changing the value of the resistor R3 remains.

IV. SIMULATION RESULTS AND EXPERIMENTAL MEASUREMENTS

To verify the behaviour of the proposed pseudodifferential second-order all-pass filter, first the SPICE simulations have been performed, where the active elements DDCCs and CCII were implemented using the macro-model of UCC-N1B integrated circuit [18], [19].

Assuming [C.sub.1] = [C.sub.2] = C and [R.sub.1] = [R.sub.2] = R, for the pole-frequency of 100 kHz and capacitors C = 1 nF, using (18), (19) the values of resistors [R.sub.1] and [R.sub.2] are 1.6 k[OMEGA]. The magnitude and phase response of the filter is shown in Fig. 3, whereas the value of the resistor R3 was 1.6 k[OMEGA] to obtain unity quality factor (i.e. Q = 1).

From the simulation results (dashed line) it can be seen that the pole-frequency has dropped to approx. 95 kHz. Such reduction in pole frequency is caused by the real properties of the active elements and could be already expected from (23), (24) since the product of the voltage and current gains is [[alpha].sub.1][[beta].sub.2][[gamma].sub.1][delta] = 0.9192 (see Table I). The pass-band gain is very close to unity (i.e. 0 dB) with the ripple of approx. 0.51 dB. The drop in magnitude at frequencies above 5 MHz is caused by the limited bandwidths of the voltage and current gains of the UCC-N1B (see Table I) that has been used to implement the required active elements' types.

In Fig. 4 the phase response for selected values of quality factor is shown. It can be seen that varying the resistor [R.sub.3] to adjust the required value of quality factor does not have any or very minor effect on the pole-frequency [f.sub.0] since for different values of Q the phase shift of -180 deg is approx. always at frequency 95 kHz. Similarly, in Fig. 5 the group delay is given where for selected values of quality factor {0.5; 1; 2} the group delay changes as {7.1; 3.6; 1.8} [mu]s.

According to (16) and using the typical values of the voltage gains [[beta].sub.1] and [[beta].sub.2] (Table I), the theoretical value of CMRR of the pseudo-differential filter is approx. 43 dB (dotted line). Note that from [9]-[13] and [15], only [13] determines the value of CMRR, which is approx. 62 dB. As can be seen from Fig. 6, the common-mode rejection ratio obtained by means of simulations (dashed line) agrees well to the expected value and is constant up to frequency approx. 1 MHz. Above this frequency the CMRR decreases, which is mainly caused by different bandwidth limitations of the corresponding voltage gains [[beta].sub.1] and [[beta].sub.1].

The behaviour of the proposed frequency filter has been evaluated also by means of experimental measurements. To perform the experimental measurements the network analyser Agilent 4392A has been used. To measure the performance of the proposed pseudo-differential filter, single-ended to differential and differential to single-ended voltage convertors have been implemented using AD8476 [20], AD8271 [21] and AD8429 [22] integrated circuits as shown in Fig. 7.

The magnitude and phase responses of the pseudodifferential filter for the values [f.sub.0] = 100 kHz and Q = 1, obtained by experimental measurements, are shown in Fig. 3 (full line) and compared to simulation results.

Also here it can be seen that the pole-frequency [f.sub.0] has dropped by approx. 5 kHz from the theoretical value, similarly as it was observed during simulations. The pass-band gain shows a ripple of approx. 1 dB and decreases significantly above the frequency 3 MHz. Such drop in magnitude is mainly caused by the bandwidth limitation of AD8476, which is 6 MHz [20].

The measured phase and group delay (full line) of the filter for the values of quality factor set to Q = {0.5; 1; 2} are shown in Fig. 4 and Fig. 5, respectively. Also here significant agreement of the measurements with the simulation results can be observed. Inaccurate values of the group delay at low frequencies are caused by the selected IF (intermediate frequency) filter bandwidth of the network analyser that has been set to 30 Hz.

The common-mode rejection ratio of the pseudodifferential filter has been also evaluated by means of experimental measurements, where the results are shown in Fig. 6 and compared to theoretical value and simulations. It can be seen that for the selected values of the quality factor the measured CMRRs are very similar. The CMRR of the filter reached by measurements has decreased from its theoretical value to approx. 36 dB. This can be due to the fact that the theoretical value of CMRR is determined using typical values of voltage gains [[beta].sub.1] and [[beta].sub.1] (Table I), whereas in case of the UCC-N1B used for measurements, the difference between [[beta].sub.1] and [[beta].sub.1] was higher.

The proposed filter has been also analysed in the time domain. In Fig. 8, the voltages [v.sub.i1] (trace 1), [v.sub.i2] (trace 2), [v.sub.o1] (trace 3) and [v.sub.02] (trace 4) of the filter are shown. The applied differential input voltage [v.sub.dm] was 10 kHz, 200 mVpp, whereas the common mode voltage [v.sub.cm] was 100 kHz, 50 mVpp. It can be seen that in the output voltages [v.sub.o1] and [v.sub.o2] the common mode signal is significantly suppressed as they mainly contain only the 10 kHz component.

V. CONCLUSIONS

In this paper new current conveyor based voltage-mode pseudo-differential second-order all-pass filter has been described. The filter uses two differential difference current conveyors and one second generation current conveyor as active elements and five passive elements--two capacitors and three resistors, whereas all are grounded. The proposed frequency filter features the possibility to control the quality factor Q independently of the angular pole-frequency [[omega].sub.0] using single resistor. Furthermore, no matching condition of passive elements is required, the filter features high input impedance and high common mode rejection ratio. The behaviour of the filter has been verified by means of SPICE simulations and furthermore, by experimental measurements. The active elements have been implemented using the integrated circuit UCC-N1B. Both the simulation and experimental results prove the functionality of the proposed filter as they agree very well to the theoretical expectations. The value of CMRR reached by simulations is approx. 43 dB, which has decreased to approx. 36 dB in case of experimental measurements, is still sufficient and hence the pseudo-differential filters can be considered as the useful function blocks for analogue signal processing.

http://dx.doi.org/10.5755/j01.eie.22.5.16344

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Jaroslav Koton (1), Norbert Herencsar (1), Jiun-Wei Horng (2)

(1) Department of Telecommunications, Brno University of Technology Technicka 3082/12, 616 00 Brno, Czech Republic

(2) Department of Electronic Engineering, Chung Yuan Christian University Chung-Li, 32023, Taiwan

koton@feec.vutbr.cz

Manuscript received 7 March, 2016; accepted 24 April, 2016.

Research described in this paper was financed by the Czech Science Foundation under grant No. 16-11460Y and National Sustainability Program under grant LO1401. For the research, infrastructure of the SIX Center was used.

TABLE I. NON-IDEAL PARAMETERS OF DDCC AND CCII
ACCORDING TO THE PROPERTIES OF UCC-N1B [18].

Gain                [-] (typical)   Bandwidth               [MHz]
                                                            (minimal)

Voltage gain            0.975       f-3dB-[[beta].sub.1]       40
  [[beta].sub.1]
Voltage gain            0.968       f-3dB-[[beta].sub.2]       46
  [[beta].sub.2]
Voltage gain            1.009       f-3dB-[[beta].sub.3]       44
  [[beta].sub.3]
Voltage gain            0.999       f-3dB-[delta]              32
  [delta]
Current gain            0.965       f-3dB-[[alpha].sub.1]      43
  [[alpha].sub.1]
Current gain            1.029       f-3dB-[[alpha].sub.2]      49
  [[alpha].sub.2]
Current gain            0.985       f-3dB-[[gamma].sub.1]      45
  [[gamma].sub.1]
Current gain            1.043       f-3dB-[[gamma].sub.2]      48
  [[gamma].sub.2]
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Author:Koton, Jaroslav; Herencsar, Norbert; Horng, Jiun-Wei
Publication:Elektronika ir Elektrotechnika
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Geographic Code:1USA
Date:Oct 1, 2016
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