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Die Attach.

"Reliability Assessment of Die Attachment Materials for High-Power Chip Package Design"

Authors: Hanxue Liu and Fei Xie; candice.liu@ relengtech.com.

Abstract: High-power chips are seen in applications such as lighting, communications and microprocessors. With power density reaching the level of 8~9W/[mm.sup.2], packaging of such chips faces increasing reliability challenges. An essential one is to maintain robust thermal dissipation, as well as a reliable electrical connection. Therefore, an assessment to determine the required material properties for die attach must be developed. This paper proposes and implements an assessment process for die-attach materials. During the preliminary package scheme selection stage, finite element method (FEM) was used for considering efficiency and cost. Key factors influencing engineering credibility of assessment such as variations of material properties, zero thermal stress setup, thermal cycle and thermal shock test conditions, and crack in the substrate attachment layer are discussed. A mechanical 3D FEA model is created matching the real dimensions of the configuration in the stackup of die, die attachment material, substrate, substrate attachment material, and heat sink. The Anand model, which describes plasticity and creep, is applied to represent the constitutive behavior. Then, this paper details a physics-of-failure approach to calculate failure cycle numbers by fatigue model based on strain energy density, which describes crack initiation and propagation. The results showed good agreement with previous study and indicated engineering credibility of assessment process. Moreover, the device under investigation is unlikely to pass a 500-cycle test given a 30% crack length as a failure criterion. It was concluded that the simulation results are credible, and influential factors such as temperature ramp rate and calculation approach are major contributors during reliability assessment. (SMTA International, September 2017)

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Title Annotation:In Case You Missed It
Publication:Printed Circuit Design & Fab Circuits Assembly
Date:Nov 1, 2017
Words:283
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