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Device characterization with an integrated on-wafer thermal probing system.


Most wireless IC applications require operation at temperatures that fluctuate widely from the ambient temperature used in the test environment. As wireless applications become more technically demanding and are driven toward higher yields, accurate device models based on temperature-dependent RF equivalent circuits become critical. Several large semiconductor companies are now monitoring or controlling chuck temperature in production for commercial applications.

Wireless applications across the world subject communications systems to temperature extremes ranging from the bitter chill of an Alaskan winter to the scalding heat of an Ecuadorian summer. Customers demand performance in these wide ranging thermal environments requiring survival of ICs both in storage and operating conditions. Characterizing the performance of these ICs over temperature is most economically accomplished at the wafer level.

Historically, high frequency on-wafer measurements over temperature have been prohibitively expensive and inefficient. Previous test set-ups have involved an assembly of probe stations, Plexi-glass dry box, probes and cables. These set-ups take weeks to install and debug since the components are autonomously designed. Since a dry box encapsulates the entire probe station, these systems also provide poor throughput due to the large volume that must be purged to avoid frost at low temperatures. Also, the issues of on-wafer calibration accuracy and stability caused by temperature-related probe and cable drift have been erroneously ignored.

Temperature-Dependent Device Models

In order for ICs or communication systems to perform effectively over temperature, accurate, temperature-dependent device models must be generated. Both silicon-and GaAs-based devices are being designed into wireless systems. Measurements of silicon bipolar devices show that |f.sub.t~ as a function of temperature can be nonlinear, as shown in Figure 1. To characterize |f.sub.t~ at any temperature accurately, parasitic pad capacitance must be determined and removed. The utilized algorithm first measures and stores a dummy device consisting of only the pads and interconnects. Subsequent measurements are calculated by subtracting the dummy from actual device data to obtain a correct |f.sub.t~. Interestingly, competing physical factors contribute to a curvilinear |f.sub.t~ response vs. temperature for a single bias point. The bias point could be adjusted to find the optimum |f.sub.t~ at any given temperature.

A thorough evaluation of a GaAs MESFET model has been presented|1~ to understand several potential temperature dependent physical factors, including the material factors, that is, energy gap, Nc, Nv and dielectric constant; the electron saturated velocities and mobilities; the contact resistance; the Schottky-barrier height and the surface potential; and the trap-related phenomena.

In summary, for the measured devices, the temperature coefficients suggest a stronger dependence of the electron velocity and a weaker dependence of the electron mobility on temperature than previously expected. The most dominant factor where the GaAs MESFET performance data are concerned is the reduction of the electron velocity with temperature. This causes |f.sub.t~ values, and thus, gain values to decrease significantly with temperature, even for devices biased at a constant current. HEMT devices also exhibit much stronger shifts in threshold voltage near 0|degree~C than MESFETs, indicating trapping effects and making derivation of linear temperature coefficients impossible, as shown in Figure 2. Thus, temperature-stable circuit designs with HEMT technology are more difficult.

Measurement Set-up and Algorithms

High frequency measurements were made at 40|degrees~, 23|degrees~, 100|degrees~ and 200|degrees~C with a thermal probing system, shown in Figure 3, and microwave probes. The 23|degrees~C measurement was repeated at the end of the sequence to verify that the device and system were stable. Transitions to sub-zero temperatures were expedient, since the thermal probing system uses a MicroChamber|TM~ environment, shown in Figure 4, enclosing only seven liters to allow purging in matter of minutes, in comparison to the hours required with traditional Plexiglass dry boxes that surround an entire probe station. At each temperature, the system was recalibrated using LRRM calibrations with automatic load inductance correction.|2~ This load inductance compensates for the micron-level misplacement of the probes on the standards to obtain the correct reference reactance. Two sets of measurements were taken over a series of bias conditions using the room temperature calibration and an at-temperature calibration. The at-temperature calibration was performed 15 minutes after making a chuck temperature change, roughly three times the thermal time constant of the probes and cables.

Calibrations were performed by contacting a separate impedance standard substrate (ISS), located on a separate thermally-isolated stage. When the main chuck is set at -65|degrees~C, the calibration chucks stabilize at -5|degrees~C, as shown in Figure 5. The calibration substrates, consisting of shorts, thrush and loads, are relatively insensitive to temperature. The element most affected by temperature is the 50 |ohms~ resistor, exhibiting a TCR of -100 ppm/|degrees~C. Therefore, worst-case deviations of the resistor for a -65 to 200|degrees~C wafer chuck excursion adds only a 0.7 percent error.

The microwave probes are constructed to withstand large thermal excursions, especially high heat. Even after prolonged exposure, the most temperature-sensitive component of the probe, the coaxial connector, is comfortably below its rated specification of 85|degrees~C, as shown in Figure 6. The air flow purge minimizes the thermal coupling between the chuck and probes and cables. TABULAR DATA OMITTED RF cables tend to exhibit significant phase changes with temperature so recalibration is generally recommended for temperature excursions of greater than 25|degrees~C.

The utilized thermal probing system offers sophisticated software algorithms for fast and easy network analyzer calibrations at temperature. To get a good comparison, the probes were left in contact with the device while the different calibration sets were recalled. This removes the unwanted effect of measurement errors caused by varying probed placement, which is the leading cause of poor on-wafer high frequency measurement repeatability. After each measurement run, a calibration stability reading was taken to understand quantitatively the changes from continued temperature setting of probes and cables. Table 1 lists the results of the measurement runs. This test requires a measurement of an open circuit so probe placement is not critical. Generally, recalibration which compensate die-to-die movements for wafer expansion effects as a function of temperature.

Effects of System Calibration on FET Temperature-Dependent Equivalent Circuits

The device used in the experiment was a 2 x 75 x 0.8 |mu~m MESFET. The layout consisted of a symmetric multifinger, ground-signal-ground arrangement with active fingers pointing in the direction of the gate-drain probe axis. Figure 8 shows the equivalent circuit for this device. Previous investigations used only a single room-temperature calibration, which may have led to erroneous derived temperature coefficients, especially for capacitances that may be susceptible to changes in transmission line lengths with temperature. Eight gate biases were measured at |V.sub.ds~ = 2 V, then three cold-FET measurements and one pinched-FET measurement were made at |V.sub.ds~ = 0 V.

The direct extraction technique|3,4~ involved three cold-FET measurements (|V.sub.g~ = 0.8, 1 and 1.2 V) to derive the source, drain and gate resistances and inductances. However, at high temperatures, the alpha-method gave inconsistent ratios of the channel-to-source resistance, forcing the value to be fixed at the room-temperature measurement. The pinched-FET measurement (|V.sub.g~ = -4 V, three volts below pinch-off) was used to estimate pad capacitances, as no dummy-FET or width-dependent capacitance data were available for this layout. The difference between | and | for the pinched FET is equal to the gate-pad capacitance |, and |C.sub.ds~ is equal to the sum of the drain-pad capacitance |C.sub.pd~ and the active-FET drain-source capacitance. The part due to |C.sub.pd~ was estimated at room temperature and the ratio of |C.sub.pd~ to the total pinched-FET value of |C.sub.ds~ was kept constant for other temperatures. Empirically, the best value of |C.sub.pd~ gives the best hot-FET |S.sub.12~ fits. Also, the resulting value of |C.sub.pd~ and | are nearly equal given the symmetric layout. The resulting direct-extracted equivalent circuit parameters had less than 3 percent variations from 1 to 26 GHz.

Figures 9 and 10 show typical temperature dependent equivalent circuit parameters for |g.sub.m~ and | at TABULAR DATA OMITTED various gate voltages (|V.sub.ds~ = 2 V). The data are quite consistent and easily fit to P(|V.sub.g~, |V.sub.ds~, T) = P (|V.sub.9~, |V.sub.ds~, |T.sub.o~)(1 + B(T - |T.sub.o~)), where |T.sub.o~ = 0|degree~C and B varies with gate and drain voltages. This FET exhibited a steep threshold-voltage shift with temperature, and as a result the |I.sub.ds~ and |g.sub.m~ values tended to have negative temperature slopes at high |V.sub.g~ (due to reduced electron saturated velocity at high temperature), whereas they show a positive slope at low |V.sub.g~, due to the lower threshold voltage.

Table 2 lists the resulting temperature coefficients B. For each parameter, B(RT) was derived using S-parameters measured with the original room-temperature calibration. B(T) was obtained by using the at-temperature calibration. The largest differences in the B coefficients are in the pad capacitances | and |C.sub.pd~, and the inductances |L.sub.d~, |L.sub.g~ and |L.sub.s~. |L.sub.s~ is not shown since its value is nearly zero. The differences in B values for |R.sub.ds~, |tau~ and |R.sub.i~ are believed to be secondarily due to pad capacitance deviations since empirical studies show that these parameters are dependent on what is assumed for these inductances and capacitances.

Generally, differences in the B coefficients are due to small differences in the extracted equivalent circuit parameters. To test their significance, a comparison to the relative change |delta~ in each parameter due to using the room-temperature or at-temperature calibration at 200|degrees~C and -40|degrees~C was performed. The S-parameters are shown in Figure 11. S-parameters for room temperature measurements done at the start and end of the session were provided in |delta~ (RT) for system stability information. If the difference in parameters at 200|degrees~ or -40|degrees~C is not much larger than |delta~ (RT), then the differences in B coefficients are insignificant. For example, | was measured at 223.8 and 224.8 fF in the room-temperature measurements, so |delta~ = 0.45 percent. At 200|degrees~C, | was extracted at 253.6 and 260.1, yielding a |delta~ = 2.6 percent. It was concluded that the difference of 9.1 and 7.3 x |10.sup.-4~/|degrees~C in B for | is significant. However, the differences in the |f.sub.t~ values and the pinched-FET value of | are not significant.


A turnkey thermal probe station can minimize the set-up and debug time needed to gather S-parameter data over temperature for equivalent circuit extractions and RF circuit designs. Simple software-aided routines and ergonomic controls make it feasible to gather data over a wide range of temperature settings to capture nonlinear effects, such as the |V.sub.t~ of a GaAs HEMT or the |f.sub.t~ of a silicon bipolar device. One-button calibrations at each measurement temperature yield more accurate FET equivalent circuit temperature coefficients, especially for the parasitic pad capacitances and inductances.


The authors would like to thank Tom Myers at Cascade Microtech for providing helpful test software modifications. The Cascade Microtech Summit Probing System was used in this article.


1. R. Anholt and S. Swirhun, "Experimental Investigation of the Temperature Dependence of GaAs FET Equivalent Circuits" IEEE Transactions on Electron Devices, September 1992.

2. A. Davidson, K. Jones and E. Strid, "LRM and LRRM Calibrations with Automatic Determination of Load Inductance," ARFTG Digest, Winter 1990.

3. R. Anholt and S. Swirhun, "The Measurement and Analysis of GaAs MESFET Parasitic Capacitances," IEEE MTT, Vol. 39, July 1991, pp. 1243-1246.

4. R. Anholt and S. Swirhun, "Equivalent-Circuit Parameter Extraction for Cold GaAs MESFETs," IEEE MTT, Vol. 39, July 1991, pp. 1247-1252.

Daniel d'Almeida received his BSEE in 1986 and his Masters of Engineering in 1987 from Cornell University. In 1987, he joined HP, where he served as product marketing engineer supporting RF vector network analyzers. In 1989, he joined Cascade Microtech as a product line manager and since 1992, has served as wafer probing product marketing manager.

Robert E. Anholt received his PhD degree from the University of California, Berkeley in 1975. He was a research associate at Stanford University in the Electrical Engineering Department, where he developed the GATES process and device modeling software. From 1976 to 1986, he was a research associate at the Stanford Physics Department. In 1988, he founded Gateway Modeling, which develops and distributes engineering software for the GaAs integrated circuit industry, including the GATES process and device modeling program, G-PISCES-2B, a two-dimensional Poisson and current-continuity equation solver, and SPECIAL, an S-parameter equivalent circuit analyzer. Anholt is a fellow of the American Physical Society.
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Title Annotation:Technical Feature
Author:d'Almeida, Dan; Anholt, Robert
Publication:Microwave Journal
Date:Mar 1, 1993
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