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Device and circuit approaches for next-generation wireless communications.

Wireless communications continue to gain importance in both the commercial arena and the military domain. However, while data rates are increasing to accommodate video and data as well as voice traffic, a conflicting need exists to reduce power consumption and extend battery lifetime. New technologies at a device and circuit level hold the promise of significantly mitigating this conflict. This article summarizes results obtained from an ongoing multi-university research program to optimize the performance of broad-bandwidth wireless communication systems. With its interdisciplinary focus, the program achieves some unique results by optimizing devices from a wireless system standpoint. The program is sponsored by the Multidisciplinary University Research Initiative (MURI) program of OSD and managed by the US Army Research Office, and involves a team of universities, including University of Michigan, UCLA, University of California, San Diego and University of Colorado. These results were reported recently in a special focused session at the International Microwave Symposium held in Baltimore, MD in June 1998.[1-4]

A key goal is to obtain an order-of-magnitude reduction in energy consumption in wireless communication systems and, as a result, a dramatic drop in the battery weight needed (which is becoming a very important issue for the soldier of the future). While battery technology itself is advancing, the increase in battery energy density over time is much slower than the overall system improvement offered by alternate approaches.

Figure 1 shows the historical drop in power consumption in representative hand-held commercial communication systems. An important factor is the reduction in battery voltage, which has decreased from 7 to 3 V over the last five years. The lower battery voltage is conducive to lower power dissipation in the digital parts of the communication system. However, lower voltage for the RF portions often means serious challenges in order to maintain power efficiency and linearity.

A variety of areas must be addressed to achieve the objective of dramatically lower power dissipation in communication systems. Modulation systems are needed that employ the lowest possible amount of energy per bit and can be implemented with efficient circuits (which tend to be nonlinear). Transistors with very low on-resistance are needed for efficient power handling with low battery voltage. Devices that are inherently more linear are needed for both transmitter and receiver use; lower noise is also important for the receiver.

Requirements also exist for improved antennas, power combiners and filters with low loss and small size and that can meet the needs of the modulation schemes employed. Reproducible fabrication and accurate models are needed to make the most of current design tools for system optimization. The trade-off between digital signal processing power efficiency and RF (analog) circuitry should be understood to permit the advances in CMOS very-large-scale integration to be used optimally.

The need for increased bandwidth in communication systems is also growing rapidly. To achieve the required rates, increasing attention is being given to high microwave and mm-wave frequencies. Current device, circuit and packaging technologies are not advanced enough to support widespread, low cost systems in this regime.

EFFICIENT POWER AMPLIFIERS

The greatest leverage for reducing the power consumption of a wireless transceiver is provided by the transmitter's output power amplifier. The MURI program has developed a number of novel concepts to increase output power amplifier efficiency while maintaining adequate linearity. New techniques for characterizing amplifier behavior with signals having complex modulation have also been developed.

Active Integrated Antennas for Class F Amplifiers

In a compact transmitter structure, integration of the power amplifier with the antenna is an attractive possibility since impedance levels can be optimized for highest efficiency rather than for connection to 50 [Omega] transmission lines as is the case in conventional systems. The resulting integrated structure is also smaller and simpler. To maximize efficiency, it is important to provide an optimal impedance to the transistor not only at the carrier frequency, but also at its harmonies. Proper amplifier design coupled with electromagnetic simulation make it possible for the antenna to present an output impedance that is optimized at all the harmonics of interest, thus yielding an integrated Class F amplifier.

For example, a GaAs MESFET-based amplifier integrated with a circular sector patch antenna is shown in Figure 2. This structure exhibits impedance vs. frequency' as shown in Figure 3, which provides optimal fundamental, second- and third-harmonic impedances for the transistor. A radiated output power efficiency of 63 percent for the combination has been obtained experimentally. While useful for FM and Gaussian minimum-shift keying, this amplifier at maximum efficiency is too nonlinear for quadrature phase-shift keying (QPSK) use. By backing off moderately from the maximum efficiency point, the active antenna has linearity sufficient for offset QPSK (IS-95 signals) with an efficiency of 43 percent.

Additional novel integrated antennas have been demonstrated that use photonic band-gap (PBG) structures to control impedances at different frequencies. The PBGs act as periodic transmission line filters that can be easily implemented in microstrip form by, for example, producing holes in the dielectric or backside ground plane, as shown in Figure 4. The PBGs should enjoy a variety of uses in the future. In this program, low loss PBGs were developed and applied to control impedances at harmonic frequencies and suppress power leakage from the amplifier to the antenna at undesired frequencies. Figure 5 shows the performance of an active antenna combining an amplifier, PBG and slot antenna, which achieves power-added efficiency (PAE) above 50 percent over an eight percent bandwidth with peak efficiency of 65 percent. In addition, these amplifiers reduce undesired harmonics that might be radiated out of the transmitter. Additional results on high efficiency power amplifiers utilizing MESFETs include an X-band, two-stage class E coplanar waveguide (CPW) amplifier using chip devices with a PAE of 37 percent and [P.sub.out] of 23 dBm, and an x-band, single-stage microstrip class F amplifier using packaged devices with a PAE of 51 percent, gain of 7 dB and [P.sub.out] of 28 dBm.

DC-to-DC Converters Incorporated into the Power Amplifier

Amplifiers often need to function over a wide range of output power levels as determined by the variable signal envelope associated with most modulation formats together with fading statistics and varying mobile-to-base station distances. For example, in IS-95 (CDMA) (although the peak output power is over 300 mW), the radiated output power is often below 1 mW and its time-average value is near 10 mW. Power amplifier efficiency typically drops rapidly at the reduced power levels, leading to low overall system efficiency.

The MURI program has addressed strategies to improve power amplifier efficiency, particularly at low power levels, which can improve the overall system efficiency dramatically. To improve the situation, the DC current, DC voltage or both must be varied as output power changes. Figure 6 shows schematically how the DC bias point of an amplifier can be varied as the power is reduced from its maximum (saturated) value. The DC bias conditions at maximum power are shown as well as desirable directions in which to vary the bias at lower output power levels.

The most straightforward way to vary the bias conditions is to alter the DC drain (or collector) current. In class AB mode, the current waveform is asymmetric and the DC average current varies automatically with output power level. In the limit of class B operation, the DC bias varies according to the square root of output power and the power efficiency varies as [P.sup.0.5] over a narrow range (albeit at some cost in linearity). Dynamic gate biasing (changing bias conditions as a function of input power by using an input signal envelope-sensitive biasing network) can be used (and has been demonstrated in several recent power amplifiers). It is also possible to vary the DC supply voltage in accordance with the output power level. The most desirable solution is to vary the DC bias current and supply voltage simultaneously.

To enable replacement of the voltage supply with the output power, small DC-to-DC converters in a technology (GaAs heterojunction bipolar transistor (HBT)) that can be integrated monolithically with the power amplifier itself have been implemented, The DC-to-DC converter employs a high switching frequency (10 to 20 MHz), which allows its output to be modulated rapidly to track the changing envelope of the output signal. Typical waveforms in cellular handsets have envelope variations in the 50 kHz to 2 MHz range, according to different standards. The high switching rate of the converter also permits small inductors and capacitors to be used in the device while minimizing tipple.

The converter uses a boost topology, providing an output voltage in the 3 to 10 V range for an input voltage of 3.3 V. The converter employs a power HBT that is capable of handling up to 1 A of current. The inductor, silicon Schottky rectifier and output capacitor are external elements. The circuit incorporates a pulse-width modulator to allow a DC input control voltage to regulate the output voltage. The converter's efficiency is dependent on the output load conditions and typically is in the 65 to 75 percent range.

The overall amplifier structure employing the DC-to-DC converter is shown in Figure 7. The input signal power is sensed with an envelope detector, which controlled the value of [V.sub.cc] for the power amplifier stage. The [V.sub.dd] voltage value was chosen to be somewhat larger than the amplitude of the RF signal swing at the drain of the device. Figure 8 shows the efficiency of the combined system as a function of output power. The value shown incorporates the inefficiency of the DC-to-DC converter as well as that of the amplifier. At the highest output power levels, the amplifier alone is more efficient since no loss is associated with the voltage converter. At lower power levels, the system with the DC-to-DC converter is superior because of its ability to optimally tailor the power supply voltage.

A significant improvement in overall efficiency results is achieved by using the DC-to-DC converter with the power amplifier because the net energy consumption of the system is dominated by the low power regime where the amplifier alone is highly inefficient. After averaging the energy consumption weighed by probability of usage, the amplifier overall efficiency was increased by a factor of 1.4. Further increases should be possible with optimized ICs, which integrate the DC-to-DC converter and power amplifier (together with an external inductor).

In general, as the input power is varied and the drain voltage of the RF output transistor changes correspondingly, the RF gain also varies. It is critical to avoid introducing distortion as a result of the power supply time dependence. To accomplish this goal and to optimize the amplifier efficiency, the gate bias voltage [V.sub.gg] is also controlled in accordance with the signal level. The overall gain can be flattened to within [+ or -]1 dB up to saturation; the resulting linearity has been shown to be adequate for IS-95 requirements.

Another possibility that is being pursued is the utilization of digital switching or a combination of digital switching and analog DC-to-DC converters to optimize the efficiency and linearity of the amplifier by properly changing the bias voltage at the collector and base of an HBT or the drain and gate of a heterostructure FET (HFET). Such switching between different battery cell voltages can result in significant efficiency and linearity enhancement even for two-stage switching. The possibility of employing integrated MEMS switches that consume very little power is being considered. A detailed analysis indicates that significant improvements in efficiency while maintaining complete linearity for class A amplifiers can be achieved with step-wise digital control,

Bandpass Delta-sigma Power Amplifiers

An additional approach to high efficiency is to use a switching-mode amplifier in which the output transistor is either on or off since it dissipates little power in either condition. A key issue is how to use such amplifiers to replicate the variable envelope signals of most wireless systems. Audio frequency class S amplifiers succeed in achieving this condition using pulse-width-modulated binary input signals. While this approach cannot be used directly in the microwave region because of the high clock frequency involved, it was determined that the output of bandpass delta-sigma modulators (BPA-[Sigma]M) can be used. Figure 9 shows an input sinusoid and the resulting binary-level and output signals after filtering. The simulated amplifier efficiency is on the order of 70 percent for 850 MHz amplification using GaAs HBTs.

MODULATION FORMAT

Overall communication system characteristics and, particularly, requirements for the RF section and digital signal processor are affected by the air interface standards and modulation approach. The trade-offs between power amplifier efficiency and distortion and their subsequent effects on the chosen modulation are important factors in the design of the overall system. For example, increasing the efficiency of the power amplifier can extend battery life. However, the improved efficiency often comes with increased distortion, which can cause increased adjacent-channel power ratio and intersymbol interference. These interference sources can limit overall system performance and must be quantified and tightly controlled.

An important issue is the choice of measurement to define the problem. Power amplifiers are commonly measured in the frequency domain using a network analyzer for small-signal measurements and a load-pull system for large-signal characterization. Two-tone measurements are used for third-order intercept point information. Communication circuits usually are measured using digital signals and a variety of modulation formats need to be studied. Useful parameters are the bit error rate, adjacent-channel power and intersymbol interference. As performance requirements increase, it is important to combine these two types of information in order to optimize the overall communications system.

A new system has been developed to combine these analog and digital techniques in a single measurement setup.[2] The input is obtained from a digital arbitrary waveform generator with a baseband bandwidth of 25 MHz. This baseband signal is mixed up to a microwave frequency between 2 and 8 GHz and amplified using a linear amplifier. The signal then is passed through the device under test, and an output attenuator and downconvertor mixer are used to recover a baseband signal. The output baseband signal is digitized for signal processing.

The entire system is operated under computer control for input waveform generation and output signal processing and analysis. The digital waveform input allows a variety of measurements, including single tone and two tone and a variety of more complex modulations, which can display the trade-offs between nonlinear amplifier operation and communications system parameters. In most cases, the amplifier can be described by a memoryless, bandpass nonlinear model. The AM and PM characteristics required for this model are measured in the time domain using a modulated signal technique with the amplifier driven into saturation.[5] Representative modulations, such as spread spectrum signals, may then be used with the same amplifier.

Figure 10 shows the resulting measured output for the nonlinear amplifier together with predicted results based on the modeling and AM-to-AM and AM-to-PM characterization of the same amplifier. All the required measurements are made with a single setup under computer control. A variety of amplifiers including class A, B, E and F are presently being investigated.

Multicarrier CDMA (MC-CDMA) systems are being studied extensively because they provide a path to broad bandwidth and can be relatively easily overlaid on regions of the spectrum already used. Such systems are being considered as part of IMT2000 (third-generation wireless systems), and are also of particular interest for defense applications because of their antijam and low probability of intercept features.

The amplifier linearity challenges within such systems are severe because the peak-to-average power ratio is particularly high. The spectral and temporal characteristics of the MC-CDMA signals were studied before and after passing through distorting amplifiers. Strategies also have been developed to mitigate the effects of the amplifiers. For example, by proper control of phase among the different carriers in the MC-CDMA signal, the peak-to-valley power ratios can be reduced by more than 4.5 dB from the conventional result (for the case of eight carriers). This improvement reduces the amount of amplifier backoff required and increases efficiency by over a factor of two.

OPTIMIZED RF TRANSISTORS

IC technology is an important driver for communication system improvements. Baseband signal processing, particularly DSP, benefits from the ongoing advance of CMOS and the associated scaling of MOSFET dimensions The evolution of transistors for the RF front end does not necessarily share the same dynamic, so the RF portion has been the focus of the MURI program.

To obtain the best performance in power amplifiers, a combination of high voltage handling capability (in excess of 10 V for 3 V power supplies) and very low on-resistance is required. Low noise and high linearity are critical features for receivers. For both cases, high carrier mobility and a high critical breakdown electric field are significant issues. Therefore, compound semiconductors (GaAs and indium phosphide (InP)) have received the greatest attention (along with SiGe). Heterojunction devices (HFETs or high electron mobility transistors (HEMT)) and HBTs are being developed in the program with the goal of optimizing their characteristics to meet wireless system requirements.

Bipolar Transistors with Reduced Saturation Charge Storage

HBTs provide the advantages of high drive capability and high power density along with high frequency response. However, if they are operated in the saturation region (such as in a switching-mode amplifier), they suffer from charge storage. In the MURI program, it has been shown that using a suitable double-HBT (DHBT) device with a wide bandgap collector and emitter can suppress this saturation charge storage.

Figure 11 shows the reverse recovery characteristics of a conventional single HBT (SHBT) and those of the new DHBTs with sinusoidal excitation. The absence of the negative-going current pulse is an indication of higher transistor speed. The GaInP DHBTs also have a lower knee voltage ([V.sub.cesat]) than their SHBT counterparts. These characteristics make them very attractive for next-generation power amplifiers. With the DHBTs, amplifier designers have more freedom to use the very low [V.sub.ce] region of transistor operation, including the switching mode, which facilitates implementation of class F, D and S amplifiers.

InP-based Ultra-high [f.sub.t] Devices

InP-based devices and monolithic ICs are good candidates for low power/low noise applications in communication systems. Extensive studies of various devices and the possibility of integration on a single chip for a transmit/receive (T/B) module are being performed. Devices based on this material system have shown good performance and are ideal for communication applications. For example, InP-based HEMTs have shown good performance in terms of noise figure, power output, low voltage operation, high efficiency and very high frequency performance. InP-based HBTs are good devices for low noise oscillators and high power/efficiency and linearity amplifiers. InP-based PIN and mixer diodes have also shown very low loss and high cutoff frequencies. Therefore, it is very prom sing, particularly for high frequency communication systems, to investigate the possibility of a monolithic T/R module based on InP technology.

To date, several devices and integration technologies in this material system have been demonstrated, including HEMT devices with 0.1 mm gate lengths with [f.sub.t]s of approximately 200 GHz and [f.sub.max]s of approximately 300 GHz; NPN-SHBTs with [f.sub.t]s in the range of 100 GHz, [f.sub.max]s of approximately 150 GHz and power levels of 1.4 mW/[mm.sup.2] with a gain of 11 dB and PAE of 43 percent; and PNP-SHBTs with [f.sub.t]s of approximately 13 GHz, [f.sub.max]s of 35 GHz and a [P.sub.out] of 0.3 mW/[mm.sup.2] with a gain of 10 dB and PAE of 24 percent. These are the best results obtained to date for PNP, InP-based transistors.

Also fabricated were NPN-DHBTs with a chirped superlattice collector region to improve the collection of carriers at the collector with [f.sub.t]s of approximately 100 GHz and [f.sub.max]s of approximately 150 GHz with a collector-to-emitter breakdown voltage [BV.sub.CEO] of 18 V and a base-to-collector breakdown voltage [BV.sub.CBO] of 23 V. These results are among the best obtained to date for these devices and render them extremely useful in high power/efficiency amplifiers.

In addition, a selective area material growth and processing technology has been developed that allows different types of devices such as HEMTs, PNP- and NPN-HBTs, and PIN and mixer diodes to be integrated monolithically on a single InP wafer. HEMT, HBT and PIN layers were grown and their performance evaluated; the results are very encouraging. This InP technology has been employed to fabricate NPN-PNP push-pull amplifiers, which yield higher linearity and better efficiency than conventional amplifiers. The NPN-PNP technology has also been employed to design very high frequency operational amplifiers that can be employed in high frequency building blocks for various types of communication circuits.

MEMS for Microwave and mm-wave Applications

Future personal and ground communications systems require very low weight and power, and small volume. In addition to decreasing size, the functionality of the platforms is necessitating the use of highly integrated RF front ends. Furthermore, in order to transmit or receive the maximum amount of data, communications systems are moving up in frequency to X-, K- and Ka-bands (10 to 40 GHz). Electronic packaging can account for up to 30 percent of the overall system mass, thus making advanced high frequency microelectronics, high density integration and packaging keys to reducing mass while improving performance.

The next leap beyond the state of the art in multichip modules for communications systems is the development of a technology that can integrate high frequency SiGe-based active devices, advanced MEMS devices and micromachined components into one wafer. Figure 12 compares a traditional X-band front end based on waveguide technology with that of an integrated MEMS-based module technology under development. To realize this vision, new concepts and advances in circuit design are needed to replace the main components of a communication system front end such as the transfer switch, diplexer, RF amplifiers, mixers, IF filters, LOs and IF amplifiers with very small, yet power-efficient, monolithic versions. The MURI program addresses the development of MEMS/Si micromachined components that can replace the passive components of an existing communication system.

Recently, Si micromachining has been used effectively for the development of low loss RF switches with insertion loss less than 1 dB in frequencies from 100 MHz to 30 GHz. These micromechanical structures require very low power and have long lifetimes and survivability. Bulk and surface Si micromachining can be used to provide a switch that delivers a speed of [10.sup.-7] to [10.sup.-6] seconds with a DC voltage of less than 3 V. Recent work at the University of Michigan has demonstrated the ability to provide a very low cost, high yield realization of this switch, as shown in Figure 13.

The use of micromachining can lead to the development of a micromachined waveguide diplexer that is excited by conventional or micromachined planar lines for compatibility with monolithic technology. This diplexer can be designed to provide performance in combination with low insertion loss and small size. Important issues such as high out-of-band attenuation and suppression of multiple bands can be addressed by the use of appropriate micromachine structures such as high Q resonators.

Two approaches have been pursued: vertically integrated filters to allow for a vertical interconnection during filtering and horizontally integrated resonators and filters for a uniplanar circuit integration. Vertically integrated cavity filters have yielded Qs of approximately 1000, narrow bandwidths of 2.5 percent and an insertion loss of approximately 0.5 dB for a 4.5 percent bandwidth at 10 GHz. Horizontally integrated membrane filters have yielded an insertion loss of 2.3 dB at 37 GHz and 3.1 dB at 62 GHz with a three percent bandwidth. Both types of filters can be monolithically integrated in microstrip or CPW transmission lines.

Crystal and surface acoustic wave (SAW) resonators are widely used for frequency selection in communication subsystems because of their high quality factor (Qs in the tens of thousands) and exceptional stability against thermal variations and aging. In particular, the majority of heterodyning communication transceivers rely heavily on the high Q of SAW and bulk acoustic wave mechanical resonators to achieve adequate frequency selection in their RF and IF filtering stages and to realize the required low phase noise and stability in their LOs.

These off-chip components often consume a sizable portion of the total subsystem area. In this respect, the devices pose an important bottleneck against the ultimate miniaturization and portability of wireless transceivers. For this reason, many research efforts are focused on strategies for either miniaturizing the components or eliminating the need for them. Recent demonstrations of microscale high Q oscillators and mechanical bandpass filters with area dimensions on the order of 30 mm x 20 mm now bring the first of these strategies closer to reality. Such devices utilize high Q, on-chip, micromechanical resonators constructed in polycrystalline silicon using IC-compatible surface micromachining fabrication techniques and featuring Qs of over 80,000 under vacuum and center frequency temperature coefficients in the range of -10 ppm/[degrees] C (several-times less with hulling techniques). To date, two-resonator micromechanical bandpass filters have been demonstrated with frequencies up to 14.5 MHz, percent bandwidths on the order of 0.2 percent and insertion losses less than 1 dB.

Figure 14 shows a photomicrograph of a typical two-resonator MEMS filter at 7.81 MHz and its measured performance with an insertion loss of [less than] 2 dB. Higher order three-resonator filters with frequencies near 455 kHz have also been achieved with equally impressive insertion losses for 0.09 percent bandwidths and with more than 64 dB of passband rejection.

CONCLUSION

This article has covered a variety of advances that can be used individually or combined to yield dramatic improvements in efficiency and bandwidth (as well as reductions in size) in broad-bandwidth wireless systems.

ACKNOWLEDGMENT

The concepts expressed here have been developed within the MURI on Low Power, Low Noise Electronics for Mobile Wireless Communication sponsored by Director, Defense Research and Engineering through the US Army Research Office and monitored by James Harvey. The authors are thankful to R. Trew for his support and direction and to numerous faculty members, industrial advisors, graduate students and researchers whose results and insights have been summarized in this article.

References

1. M. Golio, "Low Voltage Electronics for Portable Wireless Applications: An Industrial Perspective," 1998 IEEE MTT-S Digest, p. 319.

2. V. Borich, J.H. Jong, J. East and W.E. Stark, "Nonlinear Effects of Power Amplification on Multicarrier Spread Spectrum Systems," 1998 IEEE MTT-S Digest, p. 323.

3. P.M. Asbeck, T. Itoh, Y. Qian, M.F. Chang, L. Milstein, G. Hanington, P.F. Chen V. Schultz, D.W. Lee and J. Arun, "Device and Circuit Approaches for Improved Linearity and Efficiency in Microwave Transmitters," 1998 IEEE MTT-S Digest, p. 327.

4. L.P.B. Katehi, G.M. Rebeiz and C.T.C. Nguyen, "MEMS and Si-micromachined Components for Low Power, High Frequency Communication Systems," 1998 IEEE MTT-S Digest, p. 331.

5. M. Heutmaker, J. Welch and E. Wu, "Using Digital Modulation to Measure and Model RF Amplifier Distortion," Applied Microwaves & Wireless, March/April 1997, p. 34.

Peter Asbeck is a professor of electrical and computer engineering at the University of California, San Diego (UCSD). His research interests include the development of high speed heterojunction transistors and optoelectronic devices, and their circuit applications. Prior to joining UCSD, he worked at Rockwell International Science Center where he was involved in the development of high speed devices and circuits based on III-V compounds and heterojunctions.

James W. Mink received his PhD degree in electrical engineering from the University of Wisconsin in 1964. From 1964 through 1976, he was a research physical scientist for the Army at Fort Monmouth, NJ. From 1976 through 1994, Mink was employed by the Army Research Office cumulating his service as director of the Electronics Division. In addition, from 1979 through 1994 he served as the principal Army representative of the Joint Services Electronics Program. He joined North Carolina State University in 1994 on a full-time basis where he is now a visiting professor in the department of electrical and computer engineering. His research continues to focus upon mm-wave systems and devices and conformal antennas as applied to wireless communications.

Tatsuo Itoh is the TRW Endowed Chair in Microwave and Millimeter Wave Electronics at UCLA. He is also currently the director of the Joint Services Electronics Program (JSEP) and the director of the MURI program at UCLA. He was an honorary visiting professor at Nanjin Institute of Technology, China and at the Japan Defense Academy. In April 1994, he was appointed adjunct research officer for the Communications Research Laboratory, Ministry of Post and Telecommunication, Japan. He currently holds a visiting professorship at the University of Leeds, UK and is an external examiner of the graduate program of the City University of Hong Kong.

George I. Haddad is the Robert J. Hiller professor of electrical engineering and computer science at the University of Michigan and director of the Center for High Frequency Microelectronics. He served as chair of the department from 1975 to 1986 and 1991 to 1997. He also served as director of the Electron Physics Laboratory from 1969 to 1975 and director of the Solid-state Electronics Laboratory from 1986 to 1991. His expertise is in the areas of microwave and mm-wave devices and ICs, microwave-optical interaction, and optoelectronic devices and ICs.
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Author:Asbeck, Peter; Mink, James W.; Itoh, Tatsuo; Haddad, George I.
Publication:Microwave Journal
Geographic Code:1USA
Date:Feb 1, 1999
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