# Design of thermally aware ultra low power clock generator for moderate speed VLSI chip applications.

1. IntroductionIn today's era of portable electronics, sub-threshold circuits are a promising candidate to achieve ultra low power (ULP). Sub-threshold circuits quenches the demand of ultra-low power for special classes of applications like pace maker, RFID tags, wrist watches, biomedical sensors and wireless sensors--all which have moderate speed requirements and are bounded by a ULP budget (Pable and Hasan 2012; Soleman and Roy 1999). The clock circuit is one of the vital components in such applications. Current starved voltage controlled oscillator (CSVCO), configured using a CMOS-based ring oscillator, can be a good choice for clock generator circuit since it offers certain advantages like low power consumption, improved tuning range, simple architecture, low area and ease of integration (Saw and Nath 2015; Zhang and Apsel 2009). However, despite of these advantages, one of the major limitations of the ring oscillator is its sensitivity to the temperature variations leading to jitter.

The increasing demand for incorporating more and more features in the portable electronic applications has led to higher density, higher computational speed and lower cost. CMOS device dimensions are continuously shrinking to satisfy this need (Reuss and Fritze 2010). However with the enhanced features, the complexity and power consumption increase significantly and therefore power consumption has emerged as a forefront design metric. Thus, with technology scaling, the power density in advanced CMOS VLSI design is increasing, which in turn generates heat and hence leads to thermal gradient across the chip. Moreover, in order to optimise speed and power in modern VLSI chips, heterogeneous design paradigm is adapted where the conventional high performance and low power circuits are incorporated together leading to large on chip thermal gradients. The aggressive interconnect scaling further leads to higher current densities and thereby increase in chip temperature. Furthermore, the increased number of metal layers, low-K and low thermal conductivity dielectrics prevailing in the current silicon processes leads to the increase in temperature. Also, different dynamic voltage scaling and clock-gating techniques have contributed to large temperature gradients. These thermal variations further lead to unpredictable behaviour of the circuit and sometimes may even lead to circuit failure. Therefore, thermal management becomes an important concern and thermally aware design becomes the utmost of importance for reliable operation.

To investigate this effect of temperature variations, a five stage voltage controlled ring oscillator is designed at 32 nm technology node using Predictive Technology Model (Berkeley Predictive Technology Model (PTM) 2008.) and simulated in HSPICE for the super threshold (supply voltage = 0.9 V) and the sub-threshold (supply voltage = 0.3 V) region. Figure1 depicts the simulation result of variation of time period of output pulse of voltage-controlled ring oscillator with temperature at 0.9 V (super threshold) and 0.3 V (sub threshold). As evident from Figure 1, the sub-threshold ring oscillator is highly sensitive to temperature variation. The conventional super threshold voltage controlled ring oscillator shows 37% deviation in clock period with temperature variation from 10[degrees]C to 120[degrees]C, whereas 77% variation in time period of conventional sub-threshold voltage controlled ring oscillator is observed. Thus, this exponential dependency of the time period on temperature in sub-threshold regime is a major concern and therefore calls for design of thermally aware ring oscillator for reliable operation.

Substantial work to mitigate the impact of temperature variation on ring oscillators has been proposed in the conventional super threshold regime (Zhang and Apsel 2009; Reuss and Fritze 2010; Zhang, Lin, and Syrzycki 2011; Rout, Acharya, and Panda 2014; Lee and Hsieh 2008; Tsai and Huang 2012). Conventionally, the researchers have used a band gap voltage reference as well as NTC and PTC combinations to design the temperature insensitive circuits (Sundaresan and Ayazi 2006; Razavi 2000). However, the potential drawback in using band gap voltage reference is that it incorporates resistors. The sub-threshold circuits have lower sub-threshold current and therefore the resistor value is correspondingly large thereby consuming a large area. Therefore, the conventional band gap circuits are not appropriate for sub-threshold circuits. Moreover, with the NTC-PTC combination, generally we need to add an external passive component like resistor. Another technique to compensate the temperature variation is to use the feedback compensation circuit, which may cause loading effect and instability problems. Conventionally, a Phase Locked Loop (PLL) is used to provide a robust clock generator, but the loop filter design is a critical part in incorporating the PLL (Kim, Hwang, and Kang 2002; Ryu et al. 2016).

Although significant work has been carried out by the research community to combat the impact of temperature variation in the super threshold region, very few publications have explored this area in the sub-threshold regime. A ring oscillator with the delay cells biased in the weak inversion region was proposed by the researchers (Farzeen, Ren, and Chen 2010). However, this work didn't explore the thermal stability of the oscillator. Kamalinejad et al. (2014)employedthe techniqueof boosting the gate-drive voltage of CMOS transistors in pseudo-differential delay cells through the use of quasi-floating gate (QFG) architecture. However, the stability of the circuit under the temperature variations was not investigated. Rim, Choi, and Park (2012)proposeda replica module to measure the variations in clock generation scheme for sub-threshold logics. Variations were detected and the clock period was accordingly adjusted to minimise the energy consumption. Moreover, very few papers have focussed on low power temperature insensitive circuits (Ho, Li, and Wang 2013; Lasanen, Ruotsalainen, and Kostamovaara 2002; Bala and Nandy 2005; Vita, Marraccini, and Iannaccone 2007). To have temperature insensitive circuits, researchers (Ho, Li, and Wang 2013) have used the bootstrapping technique. Researchers (Lasanen, Ruotsalainen, and Kostamovaara 2002; Bala and Nandy 2005) have used external components to implement temperature insensitive circuits. Vita, Marraccini, and Iannaccone (2007)haveused comparators and S-R flip flops to have temperature insensitive circuits. However, in this work, power consumption is still several microwatts and the frequency is in KHz. Kim and Kim (2009)haveproposedalowpower temperature monitoring circuit with some transistors in sub-threshold and some in super threshold region and also the authors have used a cascode configuration in their work. Therefore to implement their circuit, two power supplies were required, which made their circuitry complicated and increased the power consumption.

Thus, the exponential dependency of clock period on temperature and increasing demand to have ultra low power circuits compels one to devise the simple techniques to design the sub-threshold ring oscillator with reduced thermal sensitivity. This work therefore proposes a simple circuit to mitigate the impact of thermal variations on output of voltage controlled ring oscillator.

The rest of the paper is organised as follows: The effect of temperature on sub-threshold circuits is explored in Section II. Section III portrays the thermal analysis of VCO. The design of proposed compensation circuit and its schematics are presented in Section IV. Finally, Section V concludes the paper.

2. Effect of temperature on sub-threshold circuits

Sub-threshold operating region has proven its suitability for energy constrained VLSI applications (Zhai, Pant, and Nazhandali et al. 2008; Kim and Roy 2003). In this domain, the sub-threshold leakage current is used as the drive current to achieve ULP.

In Weak Inversion(WI) operation, the drive current [I.sub.D] is dominated by the diffusion current in contrast with the conventional operation of the CMOS circuit where the drift current is dominant factor in contributing ID. The I-V characteristic of the NMOS transistor is depicted in Figure 2 where it can be seen that in the sub-threshold regime, the drive current exponentially depends on the input voltage. The I-V characteristics in the weak inversion region is modelled in different regions of operation as follows (Wang, Calhoun, and Chandrakasan 2006)

(1) Forward Saturation when [V.sub.DS] > 3[V.sub.t]

[mathematical expression not reproducible] (1)

(2) Conduction when [V.sub.DS] < 3[V.sub.t]

[mathematical expression not reproducible] (2)

Where,

[I.sub.0] = [mu][C.sub.ox][w/l]--(n - 1) [V.sub.t.sup.2]

[mu] is the carrier mobility, [C.sub.ox] is the gate-oxide capacitance, [V.sub.t] = [KT/q] is the thermal voltage, K is the Boltzmann constant, T is the absolute temperature, q is the elementary charge, [V.sub.th] is the threshold voltage of the MOSFET, and n is the sub-threshold slope factor.

The drive current in the sub-threshold regime exponentially depends on [V.sub.th] and [V.sub.t], the volt equivalent of temperature as indicated by (1) and (2). The temperature dependence of the threshold voltage [V.sub.th] and the mobility [mu] of the MOSFET can be given as (Weste and Harris 2010),

[V.sub.th] = [V.sub.tho] - KT (3)

[mu](T)=[mu]([T.sub.0])[([T/[T.sub.0]).sup.-m] (4)

where, [mu]([T.sub.0]) is the carrier mobility at room temperature [T.sub.0], m is the mobility temperature exponent, [V.sub.th0] is the threshold voltage at 0[degrees] K, and k is the temperature coefficient of [V.sub.th].

Due to the high gate-overdrive in the super threshold region, the mobility dominates and hence, transistors drain current (Ion) decreases with increase in temperature. In contrast with this, the sub-threshold current (ID) increases exponentially with the increase in temperature, as also seen from the simulation results in Figure 1. This leads to a deviation in the designed parameters of the circuit. For instance, the deviation in Ion leads to deviation in the delay. This deviation in delay is reflected in variation of the rising and falling pulse edges, referred to as jitter. This in turn threatens the frequency stability of clock generators. Moreover, the jitter has direct impact on the maximum operating frequency of the system because in the worst case, it decreases the usable cycle time and may result in critical path failure (Kaenel 1998). To ensure the reliable operation, a safety margin needs to be added which decreases the probability of the functional failure of the synchronous system. However, this pessimistic approach results in the degradation of performance of a well designed system (Kaenel 1998). The variation of gate delay can be larger than 300% in sub-threshold operation which prominently leads to set up time violations (Zhai et al. 2005). Therefore, to ensure the proper functionality of sub-threshold circuits in today's large thermal gradient environment, temperature insensitive circuits are a prerequisite.

3. Thermal analysis of VCO

In the conventional Current Starved Voltage Controlled Ring Oscillator (CSVCO), the current sources limit the current available to the inverter. The control voltage decides the current through the current sources and thereby the clock period.

Figure 3 shows the circuit diagram of the CSVCO. In this circuit, I1-I5 represents the CMOS inverters, while MN12-MN16 and MP12-MP16 operate as the current sinks and sources respectively. The current sources/sinks limit the current available to the inverters. The drain current of MN11 and MP11 are the same and are set by the input control voltage. The current in MN11 and MP11 is mirrored in each stage. Consequently the change in [V.sub.control] induces a global change in the output frequency of the CSVCO.

The time it takes to charge [C.sub.tot] from zero to [V.sub.SP] with the constant current [I.sub.D4] is given as (Razavi 2000)

[t.sub.1]=

t1 = [C.sub.tot][[V.sub.SP]/[I.sub.D4]] (5)

Where, [I.sub.D4] is the current flowing through the transistor MP12 and[C.sub.tot]is the load capacitance.

[t.sub.1] =[C.sub.tot][[V.sub.DD-[V.sub.SP]]/[I.sub.D1]] While the time it takes to discharge [C.sub.tot] from [V.sub.DD] to [V.sub.SP] is given by,

[t.sub.2] =[C.sub.tot][[V.sub.DD-[V.sub.SP]]/[I.sub.D1]] (6)

where [I.sub.D1] is the current flowing through the transistor MN12.

If [I.sub.D4] = ID1 =ID, then the sum of t1 and t2 is simply

[t.sub.1] + [t.sub.2] = [C.sub.tot][[V.sub.DD/[I.sub.D]] (7)

The total time period of the output pulse of the CSVCO for N (an odd number) stages and [V.sub.in] (VCO) = [V.sub.control] is given as (R.Baker 2010),

[t.sub.p] = [N*[C.sub.Tot] * [V.sub.DD]/[I.sub.D]] (8)

The drain current is governed by the control voltage in a CSVCO. Therefore, from (1) and (8),

[mathematical expression not reproducible] (9)

From (3) and (4)

[mathematical expression not reproducible]

The rate of change of the time period of a VCO with respect to temperature is

[mathematical expression not reproducible] (10)

Where

[mathematical expression not reproducible]

Equation (10) illustrates the exponential dependency of the time period of a CSVCO output on temperature in the sub-threshold regime. The negative sign in (10) indicates that the rate of change of the time period is inversely related to the change in temperature. Thus, as the temperature increases, the time period decreases and vice versa.

[mathematical expression not reproducible] Since the drain current is governed by the control voltage in a CSVCO, (9) can be written as

[mathematical expression not reproducible] (11)

Simplifying (11),

[t.sub.p] = a *exp [-[[V.sub.control]/n[V.sub.t]+[V.sub.th/[V.sub.t]](12)

a=[N*[C.sub.Tot]*[I.sub.DD]/[I.sub.0]]

Where the rate of change of the time period of a VCO with respect to the VCO input voltage [V.sub.control] is given by,

[mathematical expression not reproducible] (13)

The negative sign in (13) indicates the inverse dependency of time period on the control voltage as also illustrated by simulation result depicted in Figure 4(a,b) depicts the output frequency ofCSVCO as a function of control voltage. Thus, as the control voltage ([V.sub.control]) decreases, the total time period ([t.sub.p]) increases and vice versa. Thus, the time period of the output pulse of a CSVCO can be controlled with its control voltage.

Therefore, if the temperature variation is monitored and accordingly the control voltage is altered, the temperature variation impact on the time period of a VCO can be mitigated.

The next section focuses on the proposed control circuit which consists oftwo parts; a temperature monitoring circuit and a control voltage generator circuit.

4. Control circuit to combat temperature variation effect

Figure 5 shows the proposed control circuit to combat the effect of temperature variations. The novelty of this circuit is that all the transistors are operated in the sub-threshold regime. Also since the drain-induced barrier lowering (DIBL) is not a major problem in the sub-threshold, we have not used the cascode configuration. Moreover, a simple circuit and low power are the two major requirements of the sub-threshold circuit and the proposed circuit satisfy these requirements.

MN1, MN2, MP1 and MP2 constitutes the current mirror circuit, which gives [I.sub.1] =[I.sub.2]. The control voltage which is to be given to the voltage controlled ring oscillator is obtained at the drain terminal of transistor MN6. In order to ensure the equal source voltages of MN1 and MN2 and thereby [I.sub.1] = [I.sub.2], [V.sub.x] and [V.sub.y] are kept at the same potential. All transistors, except the MN5, are operated in the forward saturation region and transistor MN5 is operated in the non saturation (conduction) region in the sub-threshold regime. The voltage at drain terminal of MN3 is

[V.sub.y] = [V.sub.DS3] + [V.sub.DS5] (14.1)

Also

[V.sub.x] = [V.sub.DS4] (14.2)

But

[V.sub.x] = [V.sub.y] (14.3)

From (14.1), (14.2), (14.3),

[V.sub.DS4] = [V.sub.DS3] + [V.sub.DS5] (14.4)

From Figure 5[V.sub.DS4] = [V.sub.GS4]

and

[V.sub.DS3] = [V.sub.GS3] (14.5)

From (14.4) and (14.5),

[V.sub.DS5] = [V.sub.GS4] - [V.sub.GS3] (14.6)

[mathematical expression not reproducible] The current [I.sub.1] and [I.sub.2], assuming equal threshold voltages, is given as

[therefore] [V.sub.GS4] = n[V.sub.t]ln([I.sub.1]/[I.sub.01]) + [V.sub.th] (14.7)

[mathematical expression not reproducible]

[therefore] [V.sub.GS3] = n[V.sub.t]ln ([I.sub.2]/[I.sub.02]) + [V.sub.th] (14.8)

From (14.6), (14.7) and (14.8)

[therefore] [V.sub.DS5] = [V.sub.temp] = n[V.sub.t]ln ([I.sub.02]/[I.sub.01]) (14.9)

And [??][V.sub.t] = kT, it is evident from (14.9) that [V.sub.temp] is directly proportional to temperature and therefore it can be used as the temperature monitoring parameter.

MP3 and MN6 together constitute the control voltage generator circuit. The gate to source voltage of MP3 is same as MP1 and MP2. The current of NMOS transistor, MN6, is set by the control voltage [V.sub.temp] generated by the temperature monitoring circuit. Therefore as the temperature increases, the [V.sub.temp] increases which causes the drive current [I.sub.3] to increase, thereby decreasing the drain to source voltage of MN6 i.e. the control voltage and vice versa.

The overall proposed compensated CSVCO is shown in Figure 6. It is implemented at 32 nm technology node using PTM model. Table 1 specifies some of the device parameters at the 32nm technology node.

Tajalli and Leblebici (2011) experimentally and analytically showed that, scaling the supply voltage (VDD) in the deep sub-threshold region increases energy consumption and also investigated that the optimum VDD for the minimum energy consumption lies in the moderate sub-threshold region. Furthermore, Datta and Burleson (2009) explored the effect of temperature variability on the energy consumption for different VDD and device sizes. The authors (Datta and Burleson 2009) proclaimed that the sub-threshold circuits exhibit significant temperature dependence causing the [V.sub.DDmin] to be pushed to a much higher value for a higher temperature operation.

In order to investigate the optimum operating supply voltage, the proposed compensated VCO is designed at 32 nm technology node using Predictive Technology Model (PTM) model and simulated with the varying supply voltages within the sub-threshold regime. The temperature coefficient for delay and corresponding power consumption for the different supply voltages are depicted in Figure 7. Simulation results clearly indicate that as the supply voltage is increased, the temperature coefficient is reduced whereas the power consumption is correspondingly increased. At the supply voltage of 0.37V, which is still 120mv below the threshold voltage, the minimum temperature coefficient of 290ppm/[degrees]C is obtained over a wide temperature variation of 10[degrees]C to 120[degrees]C. The power consumption of the proposed VCO is 1.56[iW at room temperature. Further increase in the supply voltage causes the transistors in the proposed control voltage generator circuit to leave their determined operating region. Therefore, for the supply voltage greater than 0.37 V, an increase in the temperature coefficient and the power consumption is observed. Thus, the 0.37 V supply voltage can be considered as an optimal choice.

Figure 8 shows the linear increase in [V.sub.temp] with the increase in temperature, which exactly matches with our mathematical analysis as given by (14.9). Therefore, the [V.sub.temp] can be used as the temperature monitoring parameter.

Thus, the increase in temperature results in the increase in the output voltage oftemperature monitoring circuit ([V.sub.temp]) which in turn increases the drive current of MN6. The increase in the drive current decreases the drain to source voltage of MN6 that is the output of the control circuit. Figure 9 shows that the drain voltage of transistor MN6 decreases linearly with the increase in temperature.

Equation (10) indicates that the time period decreases exponentially with the increase in temperature and vice versa, if the higher order temperature coefficients are ignored. Furthermore, (13) illustrates that the time period increases exponentially with linear decrease in the control voltage and vice versa. Therefore, the idea is to sense the temperature using the temperature monitoring circuit. Accordingly, decrease the control voltage linearly for increase in temperature and vice versa. This adaptive control voltage is given to the control voltage terminal of the CSVCO as depicted in Figure 6 and the temperature effect on the time period of the clock pulse is thereby mitigated.

Figure 10 demonstrates the behaviour of the proposed VCO and the conventional VCO with the temperature variation at 0.37 V supply voltage. It clearly shows that the time period variation of the compensated VCO is reduced significantly over a wide range of temperature as compared to the conventional VCO.

With the control voltage of 275mv and supply voltage of 0.37V, the conventional VCO shows the delay variation with temperature coefficient of 4474ppm/[degrees]C and consumes 1.06[TW power at 40[degrees] C. On the other hand, the proposed VCO shows the delay variation with temperature coefficient of 290ppm/[degrees]C and power consumption of 1.49[iW at 40[degrees]C with 0.37V supply voltage. The proposed VCO exhibits 49.2% and 82.79% less variation in time period of output pulse and power consumption respectively compared to the conventional VCO, over a wide range of temperature variation from 10[degrees]C to 120[degrees]C. Figures 11 and 12 illustrates the variation in clock pulse width with the temperature variation for the uncompensated and the compensated VCO respectively.

Along with temperature insensitivity, the low power consumption ofthe circuit is also our concern. Therefore, the power consumption of the proposed compensated VCO is investigated and compared with the conventional sub-threshold VCO. Figure 13 demonstrates the power consumption of the compensated VCO and the conventional sub-threshold VCO. Since all the transistors in the control circuit are operated in the sub-threshold region, there is a small increase in the power consumption. With the small increase in overall power consumption, the variation in the time period of the clock pulse is controlled.

Table 2 shows the comparison of the proposed system with the reported work. Thus, the proposed compensated CSVCO proves to be a power efficient VCO with reduced temperature sensitivity, which is a major demand in applications like pace maker, RFID tags, wrist watches, biomedical sensors and wireless sensors.

5. Conclusion

The sub-threshold circuits have a huge potential to reduce the overall power consumption. However, the exponential dependency of sub-threshold circuit parameters on temperature is one of the hurdles in having reliable circuits. Today's modern technologies incorporate the heterogeneous design paradigm and therefore the thermal effect cannot be ignored. The ultra low powerclockgeneratorisanessentialcomponentfor portable VLSI computing applications. However, the variation in temperature alters the performance metrics of the clock circuit from its well designed value. Hence, it is essential to design a temperature insensitive sub-threshold clock generator. This paper presented a scheme to improve the thermal stability of the sub-threshold VCO by adaptively changing the control voltage of a voltage controlled ring oscillator without appending any passive components in the circuit. The control voltage for the VCO is adaptively manipulated based on the temperature variations. The simulation results shows that the proposed system produces stable clock frequency over a wide range of temperatures as compared to the conventional current starved VCO circuit with minimal increase in the power dissipation.

References

Baker, J. 2010. "CMOS Circuit Design Layout and Simulation (pp. 561-563)." 3rd_Edition, IEEE Press, John Wiley & Sons, Inc., Publication.

Bala, F., and T. Nandy. 2005. "Programmable High Frequency RC Oscillator." International Conference on VLSI Design 511-515. doi:10.1109/ICVD.2005.70.

Berkeley Predictive Technology Model (PTM). 2008. [Online] (Accessed September 30, 2008). http://www.eas.asu.edu/ptm

Datta, B., and W. Burleson. 2009. "Temperature Effects on Energy Optimization in Sub-Threshold Circuit Design." In Quality of Electronic Design, ISQED, IEEE. doi:10.1109/ISQED.2009.4810375.

Farzeen, S., G. Ren, and C. Chen. 2010. "An Ultra-Low Power Ring Oscillator for Passive UHF RFID Transponders." IEEE International Midwest Symposium on Circuits and Systems 558-561. doi:10.1109/MWSCAS.2010.5548887.

Gargouri, N., Z. Sakka, D. Issa, A. Kacchouri, and M. Samet. 2017. "A 4ghz Temperature Compensated CMOS Ring Oscillatorfor Impulse Radio UWB." International Conference on Sciences of Electronics, Technologies of Information and Telecommunications. doi:10.1109/SETIT.2016.7939844.

Ho, Y., K. Li, and S. Wang. 2013. "A0.3 V Low-Power Temperature Insensitive Ring Oscillator in 90nm CMOS Process." International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), IEEE.doi:10.1109/VLDI-DAT.2013.6533838.

Howard, Y., L. Lance, and S. Ramon. 1997. "A Low Jitter 0.3165 MHz CMOS PLL Frequency Synthesizer for 3V/5V Operation." IEEE Journal of Solid State Circuits 32 (4).

Kaenel, V. 1998. "A High-Speed, Low-Power Clock Generator for A Microprocessor Application." IEEE Journal of Solid-State Circuits 33 (11). doi:10.1109/4.726549.

Kamalinejad, P., K. Keikhosravy, R. Molavi, S. Mirabbasi, and V. Leung. 2014. "An Ultra-Low-Power CMOS Voltage-Controlled Ring Oscillator for Passive RFID Tags." International Conference on New Circuits and Systems, IEEE Conference on New Circuits and Systems 456-459. doi:10.1109/NEWCAS.2014.6934081.

Kim, C., I. C. Hwang, and S.-M. Kang. 2002. "A Low-Power Small-Area[+ or -]7.28-Ps-Jitter 1-Ghz DLL-based Clock Generator." IEEE Journal Solid-State Circuits 37 (11): 1414-1420. doi:10.1109/JSSC.2002.803936.

Kim, C. H., and K. Roy. 2003. "Ultra-Low Power DLMS Adaptive Filter for Hearing Aid Applications." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 11 (6): 1058-1067. doi:10.1109/TVLSI.2003.819573.

Kim, K., and Y. Kim. 2009. "A Novel Adaptive Design Methedology for Minimum Leakagr Power considering PVT Variations on Nanoscale VLSI System." IEEE Transaction on VLSI Systems 17 (4). doi:10.1109/TVLSI.2008.2007958.

Lasanen, K., E. R. Ruotsalainen, and J. Kostamovaara. 2002. "A 1-V, Self Adjusting, 5-Mhz CMOS RC-Oscillator." In Proceeding of ISCAS, Scottsdale, USA IV: 377-380. doi:10.1109/ISCAS.2002.1010469.

Lee, S., and J. Hsieh. 2008. "Analysis and Implementation of a 0.9-V Voltage-Controlled Oscillator with Low Phase Noise and Low Power Dissipation." IEEE Transactions on Circuits and Systems -II, Express Briefs 55 (7). doi:10.1109/TCSII.2008.921574.

Olmos, A. 2003. "A Temperature Compensated Fully Trimmable on Chip IC Oscillator." Integrated Circuit and System design,SBCCI 181-186. doi:10.1109/SBCCI.2003.1232826.

Pable, S. D., and M. Hasan. 2012. "A Novel Robust FPGA Routing Switch Box Design for Ultra Low Power Applications." International Journal of Electronics 99 (1): 15-27. doi:10.1080/00207217.2011.609977.

Razavi, B. 2000. Design of Analog CMOS Integrated Circuits. New York:: McGraw-Hill.

Reuss, R. H., and M. Fritze. 2010. "Introduction to Special Issue on Circuit Technology for ULP." In Proceedings IEEE 98 (2): 139-143. doi:10.1109/JPROC.2009.2037210.

Rim, W., W. Choi, and J. Park. 2012. "Adaptive Clock Generation Technique for Variation-Aware Sub-Threshold Logics." IEEE Transactions on Circuits & Systems-II 59 (9). doi:10.1109/TCSII.2012.2206933.

Rout, P., D. Acharya, and G. Panda. 2014. "A Multi-Objective Optimization Based Fast and Robust Design Methodology for Low Power and Low Phase Noise Current Starved VCO." IEEE Transactions on Semiconductor Manufacturing 27 (1). doi:10.1109/TSM.2013.2295423.

Ryu, K., J. Jung, D.-H. Jung, J. H. Kim, and S.-O. Jung. 2016. "High Speed, Low Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator." IEEE Transaction on Very Large Scale Integration (VLSI) Systems. doi:10.1109/TVLSI.2015.2453366.

Saw, S., and V. Nath. 2015. "An Ultra Low Power and Low Phase Noise Current Starved CMOS VCO for Wireless Application." International Conference on Industrial Instrumentation and Control (ICIC) 28-30. doi:10.1109/IIC.2015.7150965.

Soleman, H., and K. Roy. 1999. "Ultra-Low Power Digital Sub-Threshold Logic Circuits." In International Symposium Low Power Electronic Design, 1999 94-96. doi:10.1145/313817.313874.

Sundaresan, K., and F. Ayazi. 2006. "Process and Temperature Compensation in a 7 MHz CMOS Oscillator." IEEE Journal o/Solid-State Circuits 41 (2). doi:10.1109/JSSC.2005.863149.

Tajalli, A., and Y. Leblebici. 2011. "Design Trade-Offsin Ultra-Low Power Digital Nanoscale CMOS." IEEE Trans. Circuits Syst.-I 58 (9): 2189-2200. doi:10.1109/TCSI.2011.2112595.

Tsai, P., and T. Huang. 2012. "Integration of Current Reused VCO and Frequency Tripler for 24 GHz Low Power Phase-Locked Loop Applications." IEEE Trans. On Circuits and Systems, Express Brie/s 59 (4): 199-203. doi:10.1109/TCSII.2012.2188459.

Vita, G. D., F. Marraccini, and G. Iannaccone. 2007. "Low-Voltage Low-Power CMOS Oscillator with Low Temperature and Process Sensitivity." In Proceeding of International Symposium on Circuits and Systems, IEEE 2152-2155. doi:10.1109/ISCAS.2007.378599.

Wang, A., B. H. Calhoun, and A. P. Chandrakasan. 2006. Sub- Threshold Design /or Ultra Low-Power Systems. 1st ed. New York: Springer.

Weste, N., and D. Harris. 2010. CMOS VLSI Design A Circuits and Systems Perspective. Fourth Edition Addison-Wesley, Pearson Education Publication.

Yang, W., C. Wang, and I. Chuo. 2015. "A Robust Oscillator for Embedded Systemwithout External Crystal." International Journal on Applications Math.Inf, Sciences 9 (11): 73-80. doi:10.12785/amis/091L09.

Zhai, B., S. Hanson, D. Blaauw, and D. Sylvester. 2005. "Analysis and Mitigation of Variability in Subthreshold Design." International Symposium of Low Power Electronics and Design 05, San Diego, California, USA, August 8-10. doi:10.1109/LPE.2005.195479.

Zhai B., S. Pant, L. Nazhandali., Hanson, S., Olson, J., Reeves, A., Minuth, M., Helfand, R., Austin, T., Sylvester, D., et al. 2008. "Energy-Efficient Subthreshold Processor Design." IEEE Transactions on VLSI Systems, Vol. 17, Issue No. 8, Pp. 1127-1137. doi:10.1109/TVLSI.2008.2007564.

Zhang, C., M. Lin, and M. Syrzycki. 2011. "Process Variation Compensated Voltage Controlled Ring Oscillator With Subtractor- Based Voltage Controlled Current Source." CCECE, IEEE. doi:10.1109/CCECE.2011.6030551.

Zhang, X., and A. B. Apsel. 2009. "A Low Variation GHz Ring Oscillator with Addition Baed Current Source,"." Proceedings of ESSCIRC IEEE. doi:10.1109/ESSCIRC.2009.5325968.

Rupali Ashok Walunj, Sachin Dattatray Pable and Gajanan Kashiram Kharate

Department of Electronics and Telecommunication, Matoshri College of Engineering and Research Centre, Savitribai Phule Pune University, Nasik, India

CONTACT Rupali Ashok Walunj [??] khulers@gmail.com [??] Department of Electronics and Telecommunication, Matoshri College of Engineering and Research Centre, Savitribai Phule Pune University, Nasik, India

ARTICLE HISTORY

Received 4 March 2018

Accepted 17 May 2018

KEYWORDS

Sub-threshold; Ultra Low Power (ULP); clock generator; voltage controlled oscillator (VCO); thermal stability

https://doi.org/10.1080/1448837X.2018.1480305

Table 1. 32 nm device parameters [Berkeley Predictive Technology Model (PTM)]. Device [right arrow] Device parameters [down arrow] NMOS PMOS Threshold Voltage(V) 0.49396 -0.49155 Oxide Thickness(nm) 1.15 1.2 Table 2. Comparison of proposed system with the reported work. Olmos Bala et al. Vita et al. Parameter 2003 2005 2007 Process 0.5 um 0.18 um 0.35 um Supply voltage (V) 3 1.25 1 Frequency 12.8 6-24 0.08 (MHz) Power (uW) 133 1.12 1.14 Temp. range -40 to 125 -40 to 85 0 to 80 ([degrees]C) Temp Error 3030 N/A 842 ppm/ ppm/[degrees]C [degrees]C Ho et al. Yang et Al. Gargouri et Al. Parameter 2013 2015 2017 Process 90 nm 0.35 um 180 nm Supply voltage (V) 0.3 3.3 1.8 Frequency 235 4 4000 (MHz) Power (uW) 7 234.72 11,060 Temp. range 0 to 125 -25 to 100 0 to 120 ([degrees]C) Temp Error 89.1 986 108 ppm/ ppm/ ppm/[degrees]C [degrees]C [degrees]C Parameter Proposed Process 32nm Supply voltage (V) 0.37 Frequency 30 (MHz) Power (uW) 1.5 Temp. range 10 to 120 ([degrees]C) Temp Error 290 ppm/[degrees]C

Printer friendly Cite/link Email Feedback | |

Title Annotation: | RESEARCH PAPER |
---|---|

Author: | Walunj, Rupali Ashok; Pable, Sachin Dattatray; Kharate, Gajanan Kashiram |

Publication: | Australian Journal of Electrical & Electronics Engineering |

Date: | Mar 1, 2018 |

Words: | 5239 |

Previous Article: | Research on earth surface potential distribution and amendment for soil resistivity horizontal hierarchical model in current inflow test. |

Next Article: | Fuzzy-PID controller based on variable universe for main steam temperature system. |

Topics: |