Design of an s-band two-way inverted asymmetrical Doherty power amplifier for long term evolution applications.
With the development of modern wireless communication system, most new telecommunication technology standards, such as LTE and WiMAX, require the transmitted signals possessing a high peak to average ratio (PAR) about 8dB to achieve a high data rate transmission. Consequently, the power amplifiers must operate at a large back-off from the saturated power point to achieve high linearity. However, the efficiency is rather poor when the power amplifier working at the linear operational region. In order to increase the efficiency and linearity synchronously, the Doherty power amplifiers have been widely investigated [1-5].
Since the conventional two-way symmetrical Doherty PA exhibits the peak efficiency at a 6 dB back-off power in theory , it is not a good choice for transmitting high PAR signals Various new technologies such as two-way asymmetrical Doherty structure, N-way Doherty structure have been researched [7-9]. However, the N-way Doherty PAs result in an increase in PCB layout area and the complexity of circuit design. Thus, two-way asymmetrical Doherty PAs come to be a promising candidate for transmitting high PAR signals. On the other hand, the inserted loss of output matching network cannot be ignored because of its effect on the Doherty PA's efficiency. Therefore, the design of inverted structure, reducing inserted loss of output matching network in carrier cell is also necessary [10-13]. However, the combined use of these two effective technologies is rarely reported, especially for LTE application with large output power back-off (OPBO).
In this article, an S-band two-way inverted asymmetrical Doherty power amplifier using an unbalanced dual-path LDMOS FET is proposed. Due to the application of new Doherty structure, the proposed amplifier can achieve a peak drain efficiency of 47.6% at the 7.7dB OPBO when operating at 2.65 GHz. In addition, the LTE signal with 20-MHz channel bandwidth and 7.5 dB PAR is applied as excitation and the ACPR characteristics of the proposed amplifier are measured before and after DPD. The experiment results show that the ACPR is lower than -53dBc at an average output power of 40dBm with DPD linearization
In Section 2, the design and theoretical analysis of two-way inverted asymmetrical Doherty power amplifier is described. Implementation and the experiment results of the proposed PA are shown in Section 3. Section 4 gives the conclusion.
2. DESIGN AND ANALYSIS OF IADPA
Figure 1 shows the schematic diagram of the proposed two-way IADPA using uneven saturated power distribution. The IADPA is composed of two branches, carrier cell and peak cell, which operates in class AB and class C bias condition, respectively. The difference between IADPA and conventional asymmetrical Doherty PA is that the electric length of carrier cell output matching network, which acts as an impedance converter and also a Doherty load modulated line, has reduced from 3[lambda]/4 to about [lambda]/4.
At low input power levels, the peak amplifier is cut off because of the class C operating condition The output impedance [Z.sub.p] of peak cell, should present an open circuit state in theory to prevent power leakage by tuning the offset line [theta]p between peak amplifier and quarter-wave line. The output impedance [Z.sub.C] of carrier cell is now equal to [Z.sub.1]. And this impedance should be matched to the optimum efficiency output impedance of the device, normally known as [Z.sub.mod], for a highly efficient output at low level by tuning [[theta].sub.C]. When the input power increases and is above the transition point, the peak amplifier turns on. At this time, the carrier amplifier will be gradually saturated to keep a high efficiency while the peak amplifier provides the additional power required. When the output power reaches the saturated power of the device, [Z.sub.p] and [Z.sub.C] come to be [Z.sub.L]/[beta] and [Z.sub.L], respectively. [Z.sub.L] is the load impedance at the output of the Doherty PA (generally 50 Ohm). The output impedance [Z.sub.1] at the junction of the two branches is [Z.sub.L]/(1 + [beta]) accordingly. Equation (1) describes the variation of the output impedance [Z.sub.P] and [Z.sub.C] at different operating states. The offset line ([[theta].sub.C] - [[theta].sub.P]) before the input matching network is used to compensate the phase difference between the two branches, reducing the power-combining loss and maximizing the saturated power of the proposed IADPA.
[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] (1)
Theoretically, the optimal OPBO point with peak efficiency is determined by the saturated power ratio of the two transistors. It can be described as:
OPBO (dB) 20 log(1 + [beta]) (2)
where, [beta] is the saturated power ratio of the peak amplifier to carrier amplifier.
3. IMPLEMENTATION AND EXPERIMENTAL RESULTS
A two-way IADPA has been designed and fabricated to operate at 2.6-2.7 GHz on a 20-mil thick Rogers 4350B substrate with 3.48 dielectric constant using a high performance push-pull type LDMOS FET with 50 W P1 dB for both the carrier and peak cells. The carrier and peak amplifiers exhibit unequal saturated power of 432 dBm and 458 dBm, respectively. Hence, the saturated power ratio factor of the peak amplifier to carrier amplifier [beta] is equal to 18 approximately and the optimal OPBO point with peak efficiency in theory is 8.9 dB accordingly. However, due to the soft turn on characteristics of the realistic amplifier device used in peak cell, the practical optimal OPBO point is often smaller than the theoretical point.
The carrier cell is biased in a Class-AB condition with [V.sub.DS] = 30 V and [I.sub.DQ] 100 mA by tuning [V.sub.GS] to 2.8 V. The maximum power output impedance [Z.sub.opt] = 14.3 - j * 16.1[ohm] and optimum efficiency output impedance [Z.sub.mod] = 5.8 - j * 12.2[ohm] of the carrier amplifier at center operating frequency are determined from the loadpull data. These two impedances are conjugate matched to [Z.sub.L] and [Z.sub.1] when the proposed IADPA working at saturated power output state and low output power state with peak cell opened, respectively.
The peak cell is biased in a Class-C condition with [V.sub.DS] = 30 V and [V'.sub.GS] = 0.8 V. The maximum power output impedance [Z'.sub.opt] = 3.2 - j * 10.3[OMEGA] of the peak amplifier, also selected from the load-pull data, is matched to [Z.sub.L]/[beta] to operate in its full capacity through the impedance matching network. On the other hand, the impedance [Z.sub.1] at the junction of carrier and peak cells should be matched to the load impedance [Z.sub.L] of the proposed IADPA. Thus, a microstrip line, with characteristic impedance [Z.sub.T] ([Z.sub.T] = [square root of ([Z.sub.1] x [Z.sub.L])] and electric length of [lambda]/4, acts as an impedance converter. Table 1 depicts the values of the parameters mentioned above. Figure 2 shows the photograph of the fabricated IADPA.
A single-tone (CW) signal generated by Agilent E4438C is used to determine large signal output power, gain and drain efficiency characteristics of the proposed amplifier. Figure 3 shows the performances of gain and drain efficiency versus output power at 2.65 GHz. It is observed that the maximal drain efficiency can reach 47.6% at 7.7dB OPBO from the saturated power point of 47.7dBm. Figure 4 illustrates the drain efficiency and gain characteristics versus operating frequency at an output power of 40dBm. The measured results show that the proposed IADPA can keep a drain efficiency high than 45% and the gain fluctuation less than 0.8 dB over the operating frequency bands of 2.6-2.7 GHz.
The linearity characteristics of the proposed IADPA have been measured using a LTE signal with 20-MHz channel bandwidth and 7.5 dB PAR at 0.01% on the CCDF. Figure 5 depicts the measured power spectrum density of the proposed PA at an average output power of 40dBm before and after DPD. It is shown that an ACPR improvement of 24 dB at [+ or -]20 MHz offset is obtained after linearization. Less than -53dBc ACPR has been achieved to meet the system requirements (usually LTE system require ACPR at [+ or -]20 MHz offset less than -48dBc).
A high efficiency and linearity Doherty PA operating at 2.6-2.7 GHz is proposed in this paper. With the adoption of compact inverted load network and asymmetrical structure, the proposed PA exhibits a measured peak efficiency of 47.6% and an ACPR characteristic less than -53dBc with DPD at 7.7 dB OPBO when operating at 2.65 GHz. Besides, it keeps drain efficiencies high than 45% and gain fluctuation less than 0.8 dB over the operating frequency bands at 40dBm output power. Therefore, the proposed two-way inverted asymmetrical Doherty power amplifier can be a promising solution for LTE application.
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Hai-Jin Zhou * and Hua Feng Wu
Xi'an Electronic Engineering Research Institute, P. O. Box 132, Xi'an, Shaanxi 710100, China
Received 20 March 2013, Accepted 11 April 2013, Scheduled 13 April 2013
* Corresponding author: Hai-Jin Zhou (firstname.lastname@example.org).
Table 1. Values of mentioned parameters. [beta] [Z.sub.L] [Z.sub.1] [Z.sub.L] [Z.sub.T] /[beta] 1.8 50[ohm] 17.8[ohm] 27.7[ohm] 29.8[ohm]
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|Author:||Zhou, Hai-Jin; Wu, Hua Feng|
|Publication:||Progress In Electromagnetics Research Letters|
|Date:||Apr 1, 2013|
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