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Design of an area efficient standard cell using threshold logic NNOR cell.

INTRODUCTION

As a hard work to reduce power delay of digital CMOS circuits have been in progress for nearly three decades. As a result, a number of well understood and proven techniques for low power energy, efficient flip flop design using threshold Logic has been incorporated into new design software tools. For us, some of the customs to reduce dynamic power include logic synthesis and restructuring to reduce switching activity, gate sizing, technology Mapping, retiming, voltage scaling, and so on. Similarly, the uses of dual supply and device threshold voltages, adaptive body biasing, clock and power gating, transistor stacking, and so on are some of the well-known ways to reduce the power. Thus, it appears that the techniques for reducing power at the logic and circuit levels have been thoroughly explored, leaving minor opportunity for improvement power efficiency. Accordingly, the focus has shifted to the highest levels of design, including power efficient micro-architectures, memory, compilers, and OS, and system level control, including thermal-aware dynamic frequency and voltage control, thread migration among processor cores. One part of digital CMOS circuits that has not changed is how logic functions are computed. However, there exists a proper subset of uniting Boolean functions, called threshold functions, which can be fundamentally computed by different mechanisms, which presents the possibility of further improvements in power consumption, performance, and area, which has not been sufficiently explored.

Let X = ([x.sub.1], [x.sub.2], ..., [X.sub.n]), [x.sub.i] [member of] {0, 1}, W=([w.sub.1], [w.sub.2], ..., on), [w.sub.i] [member of] R, and T [member of] R. A unit Boolean function f (X) is called a threshold function if there exist weights w and a fixed threshold T, The reason for examining threshold gates as logic primitives stems from the fact that they are computationally more powerful than the standard AND/OR logic primitives. Much common logic functions, such as then n-bit parity, n-bit multiplication, division, powering, sorting and can be computed by polynomial size threshold networks of a fixed one of the numbers of levels, while the same would require exponential size AND/ORnetworks. the complexity of threshold networks and constructive methods for various types of arithmetic functions, including size-depth and weight depth trade offs. As results suggest that the threshold gates and networks can potentially lead to significant reductions in circuit area, power, and delay.

NMOS:

As mentioned earlier, NMOS (nMOSFET) is a type of MOSFET. An NMOS transistor is made up of n-type source and drain and a p-type substrate. When a voltage is applied to the gate, holes in the body (p-type substrate) are driven away from the gate. This allows forming an n-type channel between the source and the drain and a current is carried by electrons from source to the drain through an induced n-type channel. Logic gates and other digital devices implemented using NMOSs are said to have NMOS logic. There are three modes of operation in an NMOS called the cut-off, triode, and saturation. NMOS logic is easy to design and manufacture. But circuits with NMOS logic gates dissipate static power when the circuit is idling, since DC current flows through the logic gate when the output is low.

Neural networks of functions:

In this process simplest kind of computing units used to build artificial neural networks. These computing elements are a generalization of the common logic gates used in conventional computing and, since they operate by comparing their total input with a threshold, this field of research is known as threshold logic.

This rule implies that a McCulloch-Pitts unit can be inactivated by a single inhibitory signal, as is the case with some real neurons. When no inhibitory signals are present, the units act as a threshold gate capable of implementing many other logical functions of n-arguments. the activation function of a The unit, the so-called step function. This function changes discontinuously from zero to one at [theta]. When [theta] is zero and no inhibitory signals are present, we have the case of a unit producing the constant output one. If [theta] is greater than the number of incoming excitatory edges, the unit will never fire. In the following subsection, we assume provisionally that there is no delay in the computation of the output

Threshold logic flip-flop:

A. Basic operation:

A schematic diagram of the Threshold Logic flip-flop (TLFF) is presented in the circuit is composed of a semi-dynamic front-end comprising a differential current switch Threshold Logic gate (DCSTL) followed by a static back-end comprising an SRlatch. DCSTL front-end comprises a fast latched comparator and two parallel connected sets of unit nMOS transistors, referenced as input data bank and threshold mapping bank.

The nMOS transistors from the threshold mapping bank have the gates hardwired to ground or power supply With respect to the circuit from the TLFF h 4 data inputs and 4 threshold mapping inputs. The data inputs, [X.sub.0], [X.sub.1], [X.sub.2], x3 and the threshold mapping inputs, [T.sub.0], [T.sub.1], [T.sub.2], [T.sub.3] have the weights 1, 2, 3, 4 respectively.

In this the weights are implemented using parallel-connected sets of 1, 2, 3 and 4 unit transistors respectively. The total conductances of the transistor banks are compared each other by the latched comparator and therefore the node X is logic zero if the current generated by the data bank is greater than the current generated by the threshold mapping bank and logic one otherwise. Consider by design, the data bank is prevented from having similar conductance with the threshold mapping bank, when the threshold is reached, since an nMOS transistor with weight 0.5 is always on. This prevents the latch comparator entering in a meta-stable state.

The circuit in operates as follows. On the falling edge of the clock, the flip-flop enters in pre-charge phase. Therefore, [M.sub.10], [M.sub.11], are on, nodes X and Y are pre-charged high and the outputs Q and [Q.sub.bar] and hold their previous evaluation values; since X and Y are high, [M.sub.6], [M.sub.7] are on pulling their sources to weak high level. On the rising edge of the clock, the flip-flop enters the evaluation phase. Therefore, [M.sub.5], [M.sub.8,9] are on and [M.sub.6], [M.sub.7] (shutoff devices) start drawing currents from nodes X and Y. If Data [greater than or equal to] [I.sub.T] then the voltage at node X will start to drop faster than-than the voltage at node Y.

Databank threshold logic bank threshold logic with embedded Therefore, X crosses first the latch switching threshold which regenerates rapidly to X low and Y high, causing Q high. Conversely, if Data < [I.sub.T] then Y low and X high, causing Q low. At the end of the evaluation phase, the high-rising node among X and Y will be decoupled from being connected to ground by one of the shutoff transistors [M.sub.6], [M.sub.7] going off. Therefore no DC power is dissipated at the end of the evaluation phase. Additionally, any change on the inputs after the gate has ended the evaluation will not affect nodes X and Y and consequently, TLFF is an edge-triggered flip-flop

B. Embedding Process:

One distinctive advantage of the proposed TLFF is that complex TL functions can be embedded easily. Indeed, most logic functions available in Domino logic, such as OR/AND functions can be embedded in TLFF. Additionally, in comparison with Domino logic, wide OR/AND and their complements can be incorporated with no prohibitive latency.

D. N-NOR technology mapping:

In ASIC implementation technologies that use cell generators to create circuit elements, the set of available circuit elements consists of a parameterized family of cells rather than a specific library of functions. This cell family contains all members of a class of functions, such as And Or Inverts (AOIs), that do not exceed parameters defining the family. Library-based technology mapping is inappropriate for cell generator technologies when the number of cells in the family is too large to be practically expressed in a library.

The basis standard cell generator technology mapping is the completeness of the cell family. This simplifies the matching of network sub-functions to circuit elements. If a sub-function does not exceed the parameters defining the family, it can be implemented by a cell in the family. In addition, simplified matching makes it possible to improve the final circuit by combining decomposition and matching.

In this addresses technology mapping for a cell generator that creates NMOS or CMOS And Or Inverts gates. The set of available circuit elements includes all AOI gates that meet limits on the maximum number of transistors in series and in parallel. The network is first partitioned into a forest of trees and a circuit implementing each tree is then constructed by traversing the tree proceeding from the root node to the leaf nodes. The decomposition of each AND or OR node in the tree is determined by the parameters defining the cell family. When the in-degree of the node exceeds the limits of the cell family, the node is decomposed into a tree of nodes that match the largest available cell. When the in-degree of the node does not exceed these limits, the node is implemented by a single cell. If this cell is not the largest cell in the family, then the remaining unused capacity is passed on to the fans nodes. In Data bank threshold logic bank threshold logic with embedded Therefore, X crosses first the latch switching threshold which regenerates rapidly to X low and Y high, causing Q high. Conversely, if Data < [I.sub.T] then Y low and X high, causing Q low. At the end of the evaluation phase, the high-rising node among X and Y will be decoupled from being connected to ground by one of the shutoff transistors [M.sub.6], [M.sub.7] going off. Therefore no DC power is dissipated at the end of the evaluation phase. Additionally, any change on the inputs after the gate has ended the evaluation will not affect nodes X and Y and consequently, TLFF is an edge-triggered flip-flop

C. Embedding Process:

One distinctive advantage of the proposed TLFF is that complex TL functions can be embedded easily. Indeed, most logic functions available in Domino logic, such as OR/AND functions can be embedded in TLFF. Additionally, in comparison with Domino logic, wide OR/AND and their complements can be incorporated with no prohibitive latency.

D. n-NOR Technology Mapping:

In ASIC implementation technologies that use cell generators to create circuit elements, the set of available circuit elements consists of a parameterized family of cells rather than a specific library of functions. This cell family contains all members of a class of functions, such as And Or Inverts (AOIs), that do not exceed parameters defining the family. Library-based technology mapping is inappropriate for cell generator technologies when the number of cells in the family is too large to be practically expressed in a library.

The basis standard cell generator technology mapping is the completeness of the cell family. This simplifies the matching of network sub-functions to circuit elements. If a sub-function does not exceed the parameters defining the family, it can be implemented by a cell in the family. In addition, simplified matching makes it possible to improve the final circuit by combining decomposition and matching.

In this addresses technology mapping for a cell generator that creates NMOS or CMOS And Or Inverts gates. The set of available circuit elements includes all AOI gates that meet limits on the maximum number of transistors in series and in parallel. The network is first partitioned into a forest of trees and a circuit implementing each tree is then constructed by traversing the tree proceeding from the root node to the leaf nodes. The decomposition of each AND or OR node in the tree is determined by the parameters defining the cell family. When the in-degree of the node exceeds the limits of the cell family, the node is decomposed into a tree of nodes that match the largest available cell. When the in-degree of the node does not exceed these limits, the node is implemented by a single cell. If this cell is not the largest cell in the family, then the remaining unused capacity is passed on to the fans nodes. In this case, the cell also implements part of the functions of the fan-in nodes.

The original network is first partitioned into a forest of trees and each tree is decomposed into a minimum-depth binary number calculating as tree. The circuit implementing each number of tree is then constructed using a dynamic programming approach similar to the DAGON approach. At each node, the set of matching circuit elements is constructed using a recursive traversal that is pruned by the limits defining the cell family.

While latency is increased, the merger allows the elimination of one or more levels of logic from the path leading to the flip-flop. The result is a reduction of the overall latency of the circuit employing such a flip-flop. With regard to an 8-input AND function can be implemented in TLFF by mapping all threshold mapping inputs to Vdd. Therefore, T=8 and all data inputs have to be logic one in order to have a logic one output. An 8-input OR function can be implemented with T=1 and consequently, only one data input is necessary to be logic one in order to have a logic one output.

E. Dynamic Reconfigurability:

Another attractive advantage of TLFF is the ability to change between two evaluations the TL function embedded in TLFF. This property comes from the fact that, in contrast with other (TL) threshold mapping inputs, [T.sub.0], [T.sub.1], [T.sub.2], [T.sub.3] are accessible externally and can be treated as data inputs with negative weights.

There are presented the Spice waveforms of a reconfigurable TLFF as in Figure.3, having applied the following set of input vectors: [[X.sub.0], [X.sub.1], [X.sub.2], [X.sub.3]] = {[1, 1, 1, 1], [1, 0, 1, 1], [1, 1, 0, 1], [1, 0, 1, 0]} while threshold T is reprogrammed each four clock cycles as follows: T = 8 [right arrow] 7 [right arrow] 5 [right arrow] 3. Please note, that TLFF from Figure.3, has [OMEGA] = [1, 2, 3, 4] and T [member of] {0, 1, 2, 3, 4, 5, 6, 7, 8}., n-NOR Mapping technology After logic optimization has produced the optimized network, technology mapping selects circuit elements to implement sub-functions within this network. When wired together these circuit elements form a circuit implementing the entire network. This circuit is optimized to reduce a cost function that typically incorporates area and delay. Conventional approaches to technology mapping can be categorized as rule-based, library- based and cell generator approaches. This sections briefly describe a NNOR cell network (L&R) each of these approaches.

N-nor cell operation:

A threshold function can be implemented in the same way as any logic function, i.e., as a network of logic primitives nFETs. As implementations of a Threshold Logic Gate (TLG) considered.

In this paper compute the predicate by performing a comparison of some electrical quantity, such as charge, voltage, or current. This is what distinguishes such implementations of a threshold gate with any of the conventional implementations of CMOS logic functions. However, the use of TLGs in conventional ASIC design has not been thoroughly explored due to the lack of power energy efficient and reliable gate implementations and the infrastructure required for automated synthesis and physical design the schematic of the threshold gate with k inputs, hence forth, referred to as n-NOR.

It consists of three main components: 1) two groups of parallel pFET transistors as referred to as the Left Input Network (LIN) and the Right Input Network (RIN); 2) Sense Amplifier (SA), 3) a Set-Reset (SR) latch. The cell is operated 10 is clocked, and its behaviour can be abstracted has been that of a multi-input Edge Triggered FlipFlop, threshold logic flip-flop, otherwise conventional D-type ETFF (D-FF) computes the identity function f (x) = x on a clock edge, n-NOR cell computes a threshold function f ([x.sub.1], [x.sub.2], ..., [X.sub.n]) on a clock edge. Furthermore, like the D-FF, an n-NOR cell can be made scannable and have other features, such as asynchronous preset and clear.

1. The waveforms from the SPICE simulation of an n-NOR gate extracted from layout, NOR gate with and without transistors M9 and M10.

2. For the specific signal assignment used in the technology mapping, the maximum number of active devices in the LIN or RIN among all the functions process in that realized by an n-NOR.

3. Therefore, the simulation starts with applying a CLK-0 input, which results in N1 = 0, N2 = 1, and Q = 1. While CLK is held at 1, the input is switched to 0/5, so that n5 = HiZ1.

4. Next, N5 is discharged to ground through a capacitor, which turns OFF M5 and turns ON M7, pulling N1 to

1. This corresponds to when CLK 0 [right arrow] An input that results in l active devices in the LIN and r active devices in the RIN is denoted by l/r. The signal will ensure that l [not equal to] r. Assume that l > r

5. As a result, the conductance of the LIN is higher than that of the RIN. As the discharge devices, M18 and M19 are turned OFF, both N5 and N6 will rise to 1. discharge is impeded as M2 turns ON, resulting in N2 getting pulled back to 1. As a result, the output node N1 is 0 and N2 are 1. As the circuit, its operation is symmetric, if l < r, then the evaluation will result in N1 = 1 and N2 = 0.

For the efficiency power and analysis improvement of the Wallace tree multiplier increased from 33% and that of the FIR filter improved from 30%. Furthermore, the present results are obtained using an improved VLSI design flow that considers multiple PVT corners for tool-based optimization.

F. Scan amplifer Implementation:

If n-NOR cells are to replace flip-flops and logic cones feeding them, scan capability is essential. The simplest way to make a D-FF scannable is to use a 2:1 mux that selects between the input D and the test input (TI), depending on whether or not the test mode is enabled (TE). This is not practical for a multi-input flip-flop, such as the n-NOR cell. Although there exist several ways to implement scan for n-NORcell, In that has negligible impact on the cell's performance and robustness during normal operation. All other variations were significantly worse in this regard. The additional transistors for scan are labelled as S1 through S6. In the normal mode, the signals TE and TI are both 0, which disables the scan-related transistors (S1-S4), and reduces the circuit function in the scan mode, the TE signal itself acts as a clock. Therefore, if a circuit has a mix of D-FFs and n-NOR cells, the n-NOR cells must be part of a separate scan chain. The procedure to scan-in a stream of bits into a scan chain consisting of n-NORs is as follows. Signal global TI (GTI) is the entry point for the scan data input to the n-NOR chain.

1) Set CLK = 0 and TE = 0.

2) Set GTI = i th bit of the input (i = 0 initially).

3) Set TE = 1. Each n-NOR registers its TI input.

4) Set TE = 0.

5) Increment i and repeat until the end of stream. The pull-up transistors S5 and S6 are included to eliminate a dc path during testing. In the absence of these transistors, when TE is asserted (0 [right arrow] 1), while CLK = 0, M7 is active, and there is a dc path VDD [right arrow] M7 [right arrow] M3 [right arrow] S1 [right arrow] S2 [right arrow] GND.

Power analysis in the waveforms obtained via SPICE simulation of a scan chain of four pNAND-9 cells. The CLK is set to 0. The nodes Q1-Q4 are the output nodes of four cells that are initialized to 0. The scan pattern being registered is (Q1, Q2, Q3, Q4) = 1010.

Scanning of hybrid circuits, one with both D-FFs and n-NORs, requires two separate scan chains--one for the D-FFs and one for the n-NORs. A common TE signal is used for both the scan chains. First, the signal TE is held high, and the data are scanned into regular flip-flops.

Once this is done, the common clock signal is held low, and the data are scanned through n-NOR chain only using TE signal as described above. Note that the toggling signal TE does not affect the data stored in the first scan chain consisting of regular flip-flops. At the end of this process, both scan chains will have the required data, and regular clocking can proceed.

Advantage:

In that current research in the use of threshold logics flip-flops includes new retiming algorithms, the design of asynchronous circuits, threshold logic-based field-programmable gate arrays, nonvolatile threshold logic flipflops, and the combinations conventional logics of these different design approaches.

Conclusion:

In this experimental results shows that the proposed transistor transistor logic gates(TTL), when operated at the nominal voltage, can be made robust in the presence of process variations. However, dynamic voltage scaling, which is now an integral part of the power management of most digital circuits, must be limited when applied to threshold gates due to the presence of the latch-based SA. The degree to which the voltage of a nNOR cell can be reduced depends on k--with lower voltages for smaller k. For the 32-nm process as LTSPICE and the net list create with answer is HSPICE ,that the result is accurate. In that current research in the use of threshold logics flip-flops includes new retiming algorithms, the design of asynchronous circuits, threshold logic-based field-programmable gate arrays, non-volatile threshold logic flip-flops, and the combinations conventional logics of these different design approaches.

REFERENCES

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(1) R. Thulasimani, (2) P. Dhivya

(1) PG, Department of ECE, Vivekanandha College of engineering for women, Tiruchengode

(2) AP/ECE, Department of ECE, Vivekanandha College of engineering for women, Tiruchengode

Received 28 January 2017; Accepted 22 March 2017; Available online 28 April 2017

Address For Correspondence:

K. Thulasimani, PG, Department of ECE, Vivekanandha College of engineering for women, Tiruchengode

E-mail: thulasiece13@gmail.com

Caption: Fig. 1: McCulloch-Pitts.

Caption: Fig. 2: n-NORTechnology.

Caption: Fig. 5: Final Simulation of n-NOR cell.

Caption: Fig. 6: SR LATCH design.

Caption: Fig. 7: Simulation of SR LATCH.
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Author:Thulasimani, K.; Dhivya, P.
Publication:Advances in Natural and Applied Sciences
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Date:Apr 30, 2017
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