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Design of a low-power flash analog-to-digital converter chip for temperature sensors in 0.18 [micro]m CMOS process/Projeto de um conversor analogico-digital flash de baixa potencia para sensores de temperatura em processo CMOS a 0,18 [micro]m.

Introduction

Technological developments and use of wireless-system applications with low power consumption have become one of the main attractions in circuit design. Explosive growth of embedded sensor into radio frequency identification (RFID) tag is nowadays used with low voltage supply. Sensor data, integrated into the RFID systems, require ADC circuits. The ADC design presented in this paper is a converter suitable for a temperature sensor. The temperature sensor is implanted on the RFID-Tag chip, which is integrated into the RFID or wireless system. The design is expected to have lower power dissipation and operating voltage, small area size and easy to integrate with the other circuits. The ADC which is in accordance with that purpose is a Flash-ADC by TIQ-Comparator application. The Flash-ADC has many advantages, such as high speed, high linearity, low voltage and reduced power dissipation (YOO et al., 2003). Previous researches have undertaken a variety of methods to get the best performance of ADC, as Table 1 shows.

Table 1 shows that previous research generally developed design flash ADC with the lowest power dissipation of 1.66 [micro]W proposed by (DALY; CHANDRAKASAN, 2009). Further, (WU et al., 2012) proposed the SAR ADC design method with a power dissipation of 1200 [micro]W and (SAHOO; RAZAVI, 2009) proposed a method pipeline ADC with 348 mW power dissipation, but they did not get a lower power consumption compared to the flash ADC. Current research proposed a low power dissipation flash ADC design with TIQ-comparator, encoder and PISO register development to obtain the best performance which is compatible for use with the temperature sensor system.

Material and methods

The complete system of flash ADC consists of three main blocks, or rather, TIQ comparator, encoder and PISO registers, as shown in Figure 1.

The TIQ-Comparator is functioning as data quantization of the analog data to thermometer code (TC), and is important for linearity and accuracy of the data transfer. The encoder makes sharper thresholding of comparator output and provides full digital output voltage swing and converting to 6-bit binary code. The PISO register works to process 6bit of parallel to serial data.

The temperature sensor will use this design at a range between -100 and 200[degrees]C. The sensor has a range analog output from 285 to 560 mV with the supply voltage 1.6 V and 31.14 [micro]W power consumption. This sensor was developed on our previous research and match to input of flash ADC propose.

A basic TIQ Comparator circuit consists of two cascaded CMOS inverters, as shown Figure 2 (YOO et al., 2003). The first inverter works as voltage reference to the ADC system. The second inverter works as the gain booster to keep linearity in balance from the voltage rising and falling intervals (YOO et al., 2003).

In previous researches several methods for design of TIQ-comparator have been studied, such as: the analog input signal quantization level is set in the first stage by changing the voltage transfer curve (VTC) by transistor sizing (TANGEL; CHOY, 2004) and (SUDAKAR et al., 2011), the size of both transistor channel lengths, L and width, W are adjusted (YOO et al., 2003), third, by only adjusting W and L is fixed (TANGEL; CHOY, 2004).

Current research applies to another method by adjusting L and keeping W fixed. The advantages of this method are reduced power consumption and area of the layout. Increasing L reduces the transistor drain current, ID according to (UYEMURA, 1988) for a transistor in saturated condition as:

[I.sub.D] = 1/2 [[micro].sub.n][[epsilon].sub.ox]/[t.sub.0x] W/L [2([V.sub.GS] - [V.sub.tn]) [V.sub.DS] - [V.sup.2.sub.DS]] (1)

where:

[I.sub.D] is transistor drain current; [[micro].sub.n] is electron mobility; [[epsilon].sub.ox] is permittivity of the silicon dioxide; [t.sub.ox] is the transistor channel width layer; W is transistor channel width; L is transistor channel length; [V.sub.GS] is voltage gate-source, [V.sub.tn] is voltage threshold, [V.sub.DS] is voltage drain-source.

The main design of TIQ comparator is to convert analog data to 64-level thermometer data code as a block diagram in Figure 3. This design is referred to that to obtain n-bit flash ADC is 2n-1 comparator (KHOT et al., 2012). Therefore it is necessary to design a 6-bit Flash ADC as much as (26)-1 = 63 TIQ comparators. Meanwhile, to get the CMOS transistor channel 'L' of each first inverter refers to the mathematical expression of the threshold voltage (Vth) of any quantized sub-unit can be derived approximately as equation (2) (RAJAS HEKAR; BHAT, 2009).

[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] (2)

In this case, [V.sub.tn] and [V.sub.tp] are the threshold voltages for NMOS and PMOS devices respectively. In this equation, [K.sub.n] = [(W [L.sup.-1]).sub.n] [[micro].sub.n] [C.sub.ox] and [K.sub.p] = [(W [L.sup.-1]).sub.p] [[micro].sub.p] [C.sub.ox]. The [[micro].sub.n] and [[micro].sub.p] are the whole and electron mobility of NMOS and PMOS respectively.

Development of the comparator was based on the basic circuit given in Figure 2 and equation (2). Equation (2) was used to calculate 'L' of the PMOS transistor channel of the first inverter according to the desired value of the threshold voltage. The result is shown in Table 2. In the calculation, the range of the threshold voltage should be compatible with the output voltage of the sensor within the range 360 560 mV.

Further implementation of the design is done as follows: PMOS transistor's W on the first inverter is made on 1.4 [micro]m fixed, whereas the channel length is different and these techniques are followed to the next inverters, according to Figure 4. However, NMOS of all inverters' remain at the same ratio of W and channel L. The calculation is made starting from most significant bit (MSB) of quantized to the least significant bit (LSB) with the value of Vth, 600 to 285 mV.

In this calculation, the size of the channel L for the TIQ-comparator No. 1 to 21 only is obtained, with channel L from 0.51 [micro]m to 2.91 [micro]m, as shown in Figure 4.

For the next comparator No. 22 to 64 one or two PMOS transistors are inserted as compensation in diode connection to complement the achievement of the expected voltage input range to the lower side. The compensation transistor is inserted between VDD to the first inverter PMOS transistors, as shown in Figure 5. Meanwhile, the design size of the L and channel W of the second inverter are fixed, according to the design standard of the 0.18--[micro]m CMOS Technology. The standard design is 0.18 [micro]m of L and 1.4 [micro]m of W for PMOS and NMOS transistors respectively.

In previous researches, there are many methods for the design of the encoder circuit. There are; Fat-tree encoder (RAJESWARI et al., 2012); MUX-based encoder (ARUNKUMAR et al., 2012) and (SANDNER et al., 2005); bubble error correction (BEC) circuit; ROM-based encoder (KULKARNI et al., 2010); logic-based encoder (KUMAR; KOLHE, 2011). All the methods propose the same advantages such as high speed, high resolution, low power and etc. Logic-based encoder is the best performance and matches the proposed design. Due in this design, there are two main points that are low power and simple circuit. For the benefits of low power and simple circuit, the encoder is implementing the circuits by using CMOS logic gates in CEDEC standard library. In this process, the encoder has two functions that are used to eliminate the bubble-error and convert 64-level thermometer code into 6-bit binary code. The bubble error is the result of many sources, for instance, clock jitter, device mismatch, offset voltage. The input thermometer code of a circuit is invalid code and there is no correction circuit; consequently output of the ADC in this case is incorrect.

Circuits of the encoder proposal consist of gray code circuits and decoder circuits. The gray circuit contains NOT, AND and OR gate configuration, as Figure 6 shows.

The decoder circuits contain EXOR-gate configuration, as Figure 7 shows.

The conversion of 64-level TC into BCs is shown in Table 3. Boolean's algebra may be expressed as:

[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII].

where,

T is a thermometer code in which T64 is LSB and T1 is MSB.

G is a gray code, in which G0 is LSB and G5 is MSB. In the following expressions b is the binary code where b0 is LSB and b5 is MSB.

b5 = G5 b4 = G5 (+) G4 b3 = b4 (+) G3 b2 = b3 (+) G2 b1 = b2 (+) G1 b0 = b1 (+) G0

Parallel input serial output (PISO) register functions as converting parallel 6-bit binary to serial output as Table 4 demonstrates. The low power of shift register design was proposed by (ANDRAWES et al., 2009), where they used D flip-flop in weak inversion region. D flip-flop was used for the efficient design of the register. In this design, the PISO register circuit was configured from D-FF with load and clock control, as Figure 8 indicates. The two controls arrange data shifting into the shift-register system.

Results and Discussion

The circuit design is designed and simulated by using the tools of the Mentor Graphics Design Architect (DA) CEDEC_KIT. The design and simulations are carried out to achieve repeatedly a linear quantization value. To obtain a linear quantization value in the simulation of 0.0 V to 0.61 V, it is given by the DC input signal, as in Figure 9, while to obtain a frequency response of quantization from 1 to 10 KHz, it is given by the AC signal input, shown by Figure 10.

Figure 9 shows the conversion of analog input to quantization output responding range between 0.285 V and 0. 6 V. During the increment of 5 mV in the DC input, the quantization output increases 1 level. These phenomena are convincing to quantify the analog data temperature sensor with range between 0.36 and 0.56V only.

Figure 10 illustrates the simulated quantization result of the TIQ Comparator designed with the sinusoidal input voltage between 0V and 0.6 V-peak at the frequency 10 KHz and half wave positive transition. This graphical response exhibits a good linearity and sensitivity with linear rise and fall of the input signal.

The Encoder output graph is shown in Figure 11. This output is result simulation synchrony to Figure 8 and match to Table 3 of design principle.

Figure 12 shows simulation results of PISO registers with 6 bit binary parallel input and serial output. Pulse clock (V clock) functions as a shift control on register and pulse load (V load) for reset of the register every one byte data transfer.

Figure 13 shows simulation results of complete flash ADC with 0 to 0.6 V analog input, 100 MHz clock pulse and 10 MHz Load pulse. Simulation results show that the planning works properly so that it may change the analog data to serial linearly.

Based on Figure 13, status DC characteristic integral non linear (INL) and differential non linear (DNL) may be calculated, as shown in Figure. 14. The results show that the maximum INL is 3 mV or 0.6 LSB and maximum DNL is 2 mV or 0.4 LSB.

The final layout design chip is shown in Figure 15. This chip consists of three main blocks, or rather, TIQ-comparator, encoder and PISO register. Around the circuit is added pad terminal to connect the circuits with the power supply as well as input and output pin. All of the blocks of the flash ADC integrated in this chip, with the layout size 844.48 x 764.77 [micro][m.sup.2].

Table 5 shows the comparative results of proposed ADC with the other flash ADC architectures. It may be noted that the proposed design has the lowest power dissipation which emphasizes an innovative challenge. The layout area design was shown in Figure 14 with the pad terminal included, whereas the other designs are featured by excluding pad terminal. However, this layout size of the pad depends on the library CEDEC standard design. Hence, the proposed design did not appear in the smallest layout size in Table 5.

Conclusion

The flash ADC is designed and verified by using the Mentor Graphics VLSI Design Software. The final chip is designed by CEDEC Industry Standard I/O Cell Library for Fabrication Lab Silterra Malaysia. It consists of 64 pairs of CMOS inverters in the-TIQ comparator part, the logic based is used for the encoder part, and D-type flip-flop for the PISO register develop. The design has an input range of 285 to 600 mV and 6-bit resolution output. The chip area of the designed ADC is 844.48 x 764.77 [micro][m.sup.2]. The power dissipation is 0.162 [micro]W in 1.6 V supply voltage and the sinusoidal input voltage of 0V to 0.6 V-peak at the 10 KHz frequency and positive half wave transition condition. The design is suitable for use to the wireless temperature sensor system.

Doi: 10.4025/actascitechnol.v37i1.20870

References

AGRAWAL, N.; PAILY, R. A threshold inverter quantization based folding and interpolation ADC in 0.18 [micro]m CMOS. Journal Analog Integrated Circuits and Signal Processing, v. 63, n. 2, p. 273-281, 2010.

ANDRAWES, S.; KOUSHAEIAN, L.; VELJANOVSKI, R. Muli-threshold low power shift register International Journal of Circuits, Systems and Signal Processing v. 3, n. 1, p. 1487-1495, 2009.

ARUNKUMAR, P. C.; REKHA, G.; NARASHIMARAJA, P. Design of a 1.5-V, 4-bit flash ADC using 90nm technology. International Journal of Engineering and Advanced Technology, v. 2, n. 2, p. 274-276, 2012.

CHUN, Y. C.; LEE, M. Q.; KWANG, Y. K. A low power 6-bit flash ADC With reference voltage and common-mode calibration. IEEE Journal of Solid-State Circuits, v. 44, n. 4, p. 1041-1046 2009.

DALY, C. D.; CHANDRAKASAN, P. A. A 6-bit, 0.2 V to 0.9 V highly digital flash ADC with comparator redundancy. Ieee Journal of Solid-State Circuits, v. 44, n. 11, p. 3030-3038, 2009.

KHOT, S. S.; WANI, W. P.; SUTAONE, S. M.; BHISE, K. A 555/690 MSPS 4-bit CMOS flash ADC using TIQ comparator. International Journal of Electrical Engineering and Technology, v. 3, n. 2, p. 373-382, 2012.

KULKARNI, M.; SRIDHAR, V.; KULKARNI, G. H. The quantized differential comparator in flash analog to digital converter design. International Journal of Computer Networks and Communications, v. 2, n. 4, p. 37-45 2010.

KUMAR, P.; KOLHE, A. Design and implementation of low power 3-bit flash ADC in 0.18 [micro]m CMOS. International Journal of Soft Computing and Engineering, v. 1, n. 5, p. 71-74, 2011.

RAJASHEKAR, G.; BHAT, M. S. Design of resolution adaptive TIQ flash ADC using AMS 0.35 [micro]m technology. International Journal of Information and Communication Technology, v. 2, n. 1/2, p. 19-30, 2009.

RAJESWARI, P.; RAMESH, R.; ASHWATHA, R. A. An approach to design flash analog to digital converter for high speed and low power applications. International Journal of VLSI design and Communication Systems, v. 3, n. 2, p. 125-131, 2012.

RAJPUT, A.; KANATHE, S. Implementation of flash ADC with TIQ compareator. International Journal of Engineering and Science Research, v. 2, n. 10, p. 1462-1466 2012.

SAHOO, D. B.; RAZAVI, B. A 12-Bit 200-MHz CMOS ADC. IEEE Journal of Solid-State Circuits, v. 44, n. 9, p. 2366-2380, 2009.

SANDNER, C.; MARTIN CLARA, M.; SANTNER, A.; HARTIG, T.; KUTTNER F. A 6-bit 1.2-GS/s low-power flash-ADC in 0.13 um digital CMOS. IEEE Journal of Solid-State Circuits, v. 40, n. 7, p 1499-1505, 2005.

SENTHIL, S. M.; BANUPRIYA, M. High speed low power flash ADC design for ultra wide band applications. International Journal of Scientific and Engineering Research, v. 3, n. 5, p. 1-5, 2012.

SHAHRAMIAN, S.; VOINIGESCU, S. P.; CARUSONE, A. C. A35-GS/s, 4-bit flash ADC with active data and clock distribution trees. IEEE Journal of Solid-Statecircuits, v. 44, n. 6, p. 1709-1720, 2009.

SUDAKAR, S. C.; MANABALA, S.; BOSE, S. C.; CHANDEL, R. A new approach to design low power CMOS flash A/D converter. International Journal of VLSI design and Communication Systems, v. 2, n. 2, p. 100-108, 2011.

TANGEL, A.; CHOY, K. The CMOS inverter as a comparator in ADC designs. Journal Analog Integrated Circuits and Signal Processing, v. 39, n. 2, p. 147-155, 2004.

UYEMURA, P. J. Fundamentals of MOS digital integrated circuits reading. Boston: Addison-Wesley, 1988.

WU, H.; LI, B.; HUANG, C. W.; WANG, P. Y. A 1.2 V 8-bit 1MS/s SAR ADC with res-cap segment DAC for temperature sensor in LTE. Analog Integrated Circuits and Signal Processing, v. 73, n. 1, p. 225-232, 2012.

YOO, J.; CHOI, K.; LEE, D. Comparator generation and selection far highly linear CMOS flash analog to digital convenerter. Journal of Analog Integrated Circuits and Signal Processing, v. 2, n. 35, p. 179-187, 2003.

YOUNG, J.; HOON, K.; CHULWOO, K.; SOO-WONK, K. A5-bit 500-Ms/s flash adcusing time-domain comparison. Journal of Circuits, Systems, and Computer, v. 21, n. 8, p. 1240023/1-1240023/12, 2012.

Received on May 15, 2013.

Accepted on June 6, 2014.

Al Al*, Mamun Bin Ibne Reaz, Jubayer Jalil, Mohd Alauddin and Mohd Ali

Department of Electrical, Electronic and Systems Engineering, University Kebangsaan Malaysia, Bangi, 43600, Malaysia. * Author for correspondence. E-mail: al_mt62@yahoo.com

Table 1. Comparison of results of ADCs design.

References                       Architecture / Method

(YOO et al., 2003)               Flash / TIQ technique

(DALY; CHANDRAKASAN,         Flash / comparator redundancy
2009)

(WU et al., 2012)                    SAR / Res-Cap

(sAHOO; RAZAVI, 2009)        Pipeline / precision resistor

(kULKARNI et al., 2010)         Flash / extend the TIQ

(SHAHRAMIAN et al., 2009)         Flash / data trees

(AGRAWAL; PAILY, 2010)           Flash / TIQ technique

(RAJPUT; KANATHE, 2012)        Flash / TIQ technique and
                                      sh circuit

(SENTHIL; BANUPRIYA, 2012)        Flash / sh circuit

(CHUN et al., 2009)          Flash / reference voltage and
                                common mode calibration

(YOUNG et al., 2012)        Flash / Time domain comparator

                                         Design

References                  CMOS Technology   Supply Voltage
                              ([micro]m)           (V)

(YOO et al., 2003)               0.25         2.375 to 2.65

(DALY; CHANDRAKASAN,             0.18           0.2 to 0.9
2009)

(WU et al., 2012)                0.13              1.2

(sAHOO; RAZAVI, 2009)            0,09              1.2

(kULKARNI et al., 2010)          0.18              1.8

(SHAHRAMIAN et al., 2009)        0.35               5

(AGRAWAL; PAILY, 2010)           0.18              1.8

(RAJPUT; KANATHE, 2012)          0.35              2.5

(SENTHIL; BANUPRIYA, 2012)       0.18              1.8

(CHUN et al., 2009)              0.065             1.2

(YOUNG et al., 2012)             0.18              1.8

                                           Design

References                  Power dissipation      Layout Area
                               ([micro]W)       ([micro][m.sup.2])

(YOO et al., 2003)                35250                228

(DALY; CHANDRAKASAN,              1.66               1960000
2009)

(WU et al., 2012)                 1200                100000

(sAHOO; RAZAVI, 2009)            348000              1360000

(kULKARNI et al., 2010)           36980                 -

(SHAHRAMIAN et al., 2009)        500000                 -

(AGRAWAL; PAILY, 2010)            20000              8000000

(RAJPUT; KANATHE, 2012)           5000                  -

(SENTHIL; BANUPRIYA, 2012)        5300                  -

(CHUN et al., 2009)               4000                130000

(YOUNG et al., 2012)              8000                132000

Table 2. Calculation result of the PMOS transistor channel length
and width of the first inverter.

                           The number of the TIQ-comparator

Size                 1      2      3      4      5      6      7

Channel length,     0.51   0.54   0.58   0.62   0.66   0.71   0.78
  L ([micro]m)
Channel width,      1.4    1.4    1.4    1.4    1.4    1.4    1.4
  W ([micro]m)

                           The number of the TIQ-comparator

Size                 8      9      10     11     12     13     14

Channel length,     0.84   0.92   1.08   1.11   1.2    1.32   1.45
  L ([micro]m)
Channel width,      1.4    1.4    1.4    1.4    1.4    1.4    1.4
  W ([micro]m)

                           The number of the TIQ-comparator

Size                 15     16     17     18     19    20    21

Channel length,     1.60   1.75   1.95   2.16   2.38  2.62  2.91
  L ([micro]m)
Channel width,      1.4    1.4    1.4    1.4    1.4   1.4   1.4
  W ([micro]m)

Table 3. Thermometer code to gray code and to 6-bit code.

                               Thermometer Code

No.   T64    T63    T62     -     T32          T4     T3     T2     T1

1      0      0      0      -      0    -      0      0      0      0
2      0      0      0      -      0    -      0      0      0      1
3      0      0      0      -      0    -      0      0      1      1
4      0      0      0      -      0    -      0      1      1      1
5      0      0      0      -      0    -      1      1      1      1
-      -      -      -      -      -    -      -      -      -      -
32     0      0      0      0      1    1      1      1      1      1
-      -      -      -      -      -    -      -      -      -      -
62     0      0      1      -      1    -      1      1      1      1
63     0      1      1      -      1    -      1      1      1      1
64     1      1      1      -      1    -      1      1      1      1

                    Gray Code

No.    G5     G4     G3     G2     G1     G0

1      0      0      0      0      0      0
2      0      0      0      0      0      1
3      0      0      0      0      1      1
4      0      0      0      0      1      0
5      0      0      0      1      1      0
-      -      -      -      -      -      -
32     1      0      0      0      0      0
-      -      -      -      -      -      -
62     1      1      0      0      1      1
63     1      1      0      0      0      1
64     1      1      0      0      0      0

                 6-bit binary

No.    b0     b1    b2    b3    b4     b5

1      0      0     0     0     0      0
2      0      0     0     0     0      1
3      0      0     0     0     1      0
4      0      0     0     0     1      1
5      0      0     0     1     0      0
-      -      -     -     -     -      -
32     1      0     0     0     0      0
-      -      -     -     -     -      -
62     1      1     1     1     0      1
63     1      1     1     1     1      0
64     1      1     1     1     1      1

Table 4. Parallel 6-bit binary to serial on 1 byte data.

       Parallel Data Input

CLK     B5      B4    B3   B2   B1    B0      Serial
       (MSB)                         (LSB)    Output

0        1      0     1    0    1      0        X
1        X      1     0    1    0      1      0 LSB
2        X      X     1    0    1      0        1
3        X      X     X    1    0      1        0
4        X      X     X    X    1      0        1
5        X      X     X    X    X      1        0
6        X      x     X    X    X      X      1 MSB

Table 5. Comparison of the propose design with other flash
ADCs.

                                                 Design

References           Architecture      CMOS      Supply       Power
                          /         Technology   Voltage   dissipation
                        Method      ([micro]m)     (V)     ([micro]W)

(YOO et al., 2003)   Flash / TIQ       0.25       2.375      35,250
                      technique                  to 2.65

(DALY;                 Flash /                   0.2 to
CHANDRAKASAN,         comparator       0.18                   1.66
2009)                                              0.9
                      redundancy

(KULKARNI et al.,      Flash /
2010)                 extend the       0.18        1.8       36,980
                         TIQ

(SHAHRAMIAN          Flash / data      0.35         5        500,000
et al., 2009)           trees

(AGRAWAL; PAILY,     Flash / TIQ       0.18        1.8       20,000
2010)                 technique

(RAJPUT;             Flash / TIQ       0.35        2.5        5000
KANATHE, 2012)        technique
                        and sh
                       circuit

(SENTHIL;             Flash / sh       0.18        1.8        5300
BANUPRIYA, 2012)       circuit

(CHUN et al.,          Flash /        0.065        1.2        4,000
2009)                 reference
                     voltage and
                        common
                         mode
                     calibration

(YOUNG et al.,       Flash / Time
2012)                   domain         0.18        1.8        8,000
                      comparator

Proposed design      Flash / TIQ       0.18        1.6        0.162
                      Comparator

                           Design

References                 Layout
                            Area
                     ([micro][m.sup.2])

(YOO et al., 2003)          228

(DALY;
CHANDRAKASAN,            1,960,000
2009)

(KULKARNI et al.,
2010)                        --

(SHAHRAMIAN                  --
et al., 2009)

(AGRAWAL; PAILY,         8,000,000
2010)

(RAJPUT;                     --
KANATHE, 2012)

(SENTHIL;                    --
BANUPRIYA, 2012)

(CHUN et al.,             130,000
2009)

(YOUNG et al.,
2012)                     13,2000

Proposed design           645,832
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Date:Jan 1, 2015
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