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Design of 8-Bit shift register using power Pc-style flip flop.

INTRODUCTION

The modem digital systems impose constraints low power, less area occupation and high speed circuits. The design of clock plays a major role in communication system. The pulsed clock signal is used to increase the data rate of the system designed.

In literature, the design of various Latches and Flip-Flops is performed. The basic difference between the latch and flip-flop lies at the enable signal and the clock signal. The enable signal is used to trigger the latch that is level sensitive. While the clock signal is used to trigger the Flip-Flop, which is edge triggered. The edge triggering can be done by using rising edge or falling edge. But most practical circuits use positive or rising edge triggered flip-flops.

The basic design of the flip-flop is shown in fig.1[1], where two latches are used to design the flip-flop. The output signal is given to a delay circuit for generation of pulsed clock signal to derive the short width pulses.

The fig.2 shows the design of generic and multi-bit pulsed latch. From the generic pulsed latch structure, the pulses can be easily distorted since the pulse generator and Latches are placed apart. In multi-bit pulsed latches, the pulse generator and latches are placed and hard-wired together in a compact and symmetric form. Also the pulse distortion and clock skew can be well controlled.

In fig.3.(a), when the applied clock signal, CLK is 0, the PMOS transistor P1 and the NMOS transistor N1 turn on which causes pulse clock PCK to be 0. Also the pull-down network is enabled after N2 is turned on at the rising edge of CLK, and hence the PCK signal at the output is driven high. Both the transistors N3 and P2 are subsequently turned on, which drives the PCK signal back to 0.

Hence, the pulse width is determined by the inverter chain delay. And if the clock gating, driven by signal EN (enable) is embedded in the circuit, the enable signal EN is not allowed to change while the PCK signal is 1, which occurs briefly, and can be realized by a simple transmission gate. This signal is utilized in the fig.3 (b) for the implementation of pulsed Flip-Flop.

The 8-bit shift register uses the D-Flip Flop driven a clock pulse signal. The shift registers are used in applications like digital filters, communication systems and image processing ICs. The Design of Flip Flop plays a crucial role in the storage buffers. The proven ways used to design a memory element are shown in fig.4.

In fig.4.(a), the master slave flip flop is designed by using two latches driven by synchronous clock. In fig.4.(b), the pulsed latch is driven by a pulse generation circuit as shown in fig.5.

The fig.5, the delayed pulsed clock generator is designed by using CMOS technology with the standard W/L ratio as 3:1. For delayed pulsed clock generator includes a delay element, two inverters and a AND gate.

latch and Flip-Flop:

This paper utilizes a the Power PC Style Flip Flop(PPCFF) and static Differential Sense Amplifier Shared Pulse Latch (SSASPL). The novel SSASPL with 9 transistors 6] is adapted to the SSASPL with 7 transistors as shown in Fig.3 by removing an inverter to generate the complementary data input (Db) from the data input (D). The SSASPL uses the minimum number of transistors (7 transistors) and it consumes the lowest clock power because it has a single transistor driven by the pulsed clock signal. Three NMOS transistors are used to update the data which holds the data with four transistors in two cross-coupled inverters [11]. Two differential data inputs (D and Db) and a pulsed clock signal is required. Data is updated when the pulsed clock signal is in high position According to the input data (D and Db) the node Q or Qb is pulled down to ground. The pull-up current of the PMOS transistors is lesser than the Pull-down current of the NMOS transistors in the inverters.

The PPCFF uses 16 smallest number of transistors which are among the flip-flops [10]-[15]. The schematic of the PPCFF, shows in Fig.4. Which is a master-slave flip-flop composed of two latches. The PPCFF contains 16 transistors, in addition 8 transistors are used to driven clock signals. PPCFF uses the minimum size of transistors for a fair comparision.

shift register design:

For small area and low power consumption, shift register uses pulsed latch as an striking solution [8]. Due to the timing problem, pulsed latch cannot be used in shift registers as shown in Fig.8. The shift register in Fig 8(a) contains several latches and a pulsed clock signal(CLK pulse). The timing problem in the shift register is shown in the operation waveforms in Fig 8(b). The input signal of the first latch (IN) is constant due to this the output signal of the first latch(Q1) changes correctly [12]. The input signal (Q1) varies during the clock pulse width due to this reason the second latch has an uncertain output signal(Q2).

To minimize the timing problem, the best solution is to add delay circuits between latches, as shown in Fig. 9(a). latch's output signal is delayed and reaches next latch after the clock pulse. During the clock pulse width, the output signals of the first and second latches (Q1 and Q2) changes. Due to this effect, the input signals of all latches during clock pulse remains constant and also no timing problem occurs between the latches. Even-though, the delay circuits cause large area and power overheads [16].

The possible solution is to use multiple non-overlap delayed pulsed clock signals, as shown in Fig 10(a). when a pulsed clock signal goes through delay circuits, the delayed pulsed clock signals are generated. Every latch utilizes a pulsed clock signal which is delayed from the pulsed clock signal used in the next latch [9]. So, every latch updates the information after its next latch updates the information. End result, each latch has a constant input during its clock pulse and there is no timing problem arises between latches [13]. Many delay circuits are also required for this solution [14]. The respective waveforms are as shown in fig. 10(b)

The proposed shift register is an example which is shown in Fig. 11(a). To reduce the number of delayed pulsed clock signals, the proposed shift register is divided into sub M shift registers. Five latches are present in the 4 BIT Shift register with five non-overlap delayed pulsed clock signals (CLK_pulse<1:4> and CLK_pulse<T>) [10]. Four latches store 4-bit data i.e.,(Q1-Q4),in the 4-bit sub shift register #1, and the 1 bit temporary data (T1) stores in the last latch [15]. The resustored in the first latch(Q5) of the 4 bit sub shift register #2. Fig 11(b) shows the proposed shift register with operation waveforms.

RESULTS AND DISCUSSION

All the corresponding designs of Flip-Flops, latches and Shift registers are designed in SPICE and verified in Synopsys HSPICE Tools. Avan waves is used to visualize the simulated outputs. The designs are compared for power, delay and power Delay Product. The delayed pulsed clock generator produced a overall delay of 0.1952nS with a overall power consumption of 75.566mW.

The simulated waveforms are shown in figs. 12 and 13 for the Master Slave Flip Flop and Pulsed Latch. As per the requirement the signals are generated. In fig.12, the master-slave Flip Flop results in the output with minimum delay even though two latches are used to develop it. While the clock is rising, with the help of latch, the pulsed clock is generated as shown in fig. 13. When compared to Master Slave Flip Flop, the pulsed latch has better shape of waveform and performance.

The Table I shows the comparison result of Master Slave Flip Flop and Pulsed Latch. The delay is decreased by 47.4% in Pulsed Latch. The power consumption is improved by 6.9%. The Power Delay Product of pulsed latch is found to be improved by 67.45% in pulsed latch when compared with master slave flip flop. Also the area is improved by 42.1% in pulsed latch than in Master Slave D-Flip Flop.

The simulated waveforms are shown in figs. 13 and 14 for the SSASPL and PPCFF. The output of the SSAPL flip-Flop is degraded as the logic levels are not clearly distinguishable. But in PPCFF, the output has minimum delay with good shape of waveform and desired performance.

The Table II shows the comparison result of SSASPL and PPCFF. Even though the delay is increased and the power consumption is decreased, the Power Delay Product of SSASPL is found to be improved by 85.6% than PPCFF. As Trade-off exists for area and figure of merit, the increase in area is acceptable.

The simulated waveforms are shown in figs. 16, 17, 18 and 19 for 8-bit Shift Registers for the circuits in figs. 8,9,10 and 11 respectively. Among these the output is in good shape and clear for logic levels for proposed 8-bit shift register. The Table III shows the comparison result of various combinations of 8-bit shift register

The Table.III shows the comparison results of the all combinations of 8-bit shift registers. The Power Delay Product is found to be improved by 36.5% from design1, 39.74% and 41.19% from design3 respectively. Due to Trade-off between the Area and figure of merit, the increase in area occupied by transistors is acceptable and further if compensation is required scaling of transistor size can be done.

Conclusion:

The shift registers prove to be the essential components of Digital Filters, image processing ICs etc. The timing problem in the conventional shift registers is overcome by multiple non -overlap delayed pulsed clock signals. The pulsed latches used in the design are area and power efficient. The 8-bit shift register is designed by grouping the latches to several sub shift registers and with additional temporary storage latches. The Designs are developed in SPICE and verified in Synopsys HSPICE Tools. The Power Delay Product of pulsed latch is found to be improved by 67.45% in pulsed latch and master slave flip flop. The Power Delay Product of SSASPL is found to be improved by 85.6% than PPCFF. The Power Delay Product is found to be improved by 36.5% from design1, 39.74% and 41.19% from design3 respectively.

REFERENCES

[1.] Youngsoo Shin, Seungwhun palk, 2011. "Pulsed-Latch Circuits: A new dimension in ASIC Design," IEEE Design and Test of Computers, pp: 50-57.

[2.] Byung-do Yang, 2015. "Low Power and Area Efficient Shift Register using Pulsed latches", IEEE Transactions on Circuits and Systems I: Regular Papers, 62(6): 1564-1571.

[3.] Harshit Singh, M. Meenalakshmi, Shyam Akashe, 2016. "Power efficient shift register using FinFET technology", Emerging Trends in Electrical Electronics & Sustainable Energy Systems (ICETEESES) International Conference on, pp: 318-321.

[4.] Archana, A., S. Uma Maheswari, 2016. "Analysis of DICE latch based shift register", Circuit Power and Computing Technologies (ICCPCT) 2016 International Conference on, pp: 1-5.

[5.] Ettore Napoli, Gerardo Castellano, Davide De Caro, Darjn Esposito, Nicola Petra, Antonio G.M. Strollo, 2017. "A SISO Register Circuit Tailored for Input Data with Low Transition Probability", Computers IEEE Transactions on, 66: 45 -51.

[6.] Dinesh, S., Christo Ananth, 2015. "Area power and speed optimized serial type daisy chain memory using modified CPG with SSASPL", Control Instrumentation Communication and Computational Technologies (ICCICCT) 2015 International Conference on, pp: 344-349.

[7.] Poorna Marthi, Nazir Hossain, Huan Wang, Jean-Frangois Millithaler, Martin Margala, Ignacio Iniguez-dela-Torre, Javier Mateos, Tomas Gonzalez, 2016. "Design and Analysis of High Performance Ballistic Nanodevice-Based Sequential Circuits Using Monte Carlo and Verilog AMS Simulations", Circuits and Systems I: Regular Papers IEEE Transactions on, 63: 2236-2244.

[8.] Yamasaki, H., T. Shibata, 2007. "A real-time image-feature-extraction and vector-generation vlsi employing arrayed-shift-register architecture", IEEE J. Solid-State Circuits, 42(9): 2046-2053.

[9.] Heo, S., R. Krashinsky, K. Asanovic, 2007. "Activity-sensitive flip-flop and latch selection for reduced energy", IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 15(9): 1060-1064.

[10.] Partovi, H. et al., 1996. "Flow-through latch and edge-triggered flip-flop hybrid elements," IEEE Int. Solid -State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp: 138-139.

[11.] Consoli, E., M. Alioto, G. Palumbo and J. Rabaey, 2012. "Conditional push -pull pulsed latch with 726 fJops energy delay product in 65 nm CMOS," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp: 482-483.

[12.] Stojanovic, V. and V. Oklobdzija, 1999. "Comparative analysis of masterslave latches and flip-flops for high-performance and low-power systems," IEEE J. Solid-State Circuits, 34(4): 536-548.

[13.] Montanaro, J. et al., 1996. "A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor," IEEE J. Solid-State Circuits, 31(11): 1703-1714.

[14.] Nomura, S. et al., 2008. "A 9.7 mW AAC-decoding, 620 mW H.264 720p 60fps decoding, 8-core media processor with embedded forwardbody-biasing and power-gating circuit in 65 nm CMOS technology," in IEEE Int. Solid-State Circuits Conf. (iSsCC) Dig. Tech. Papers, pp: 262-264.

[15.] Partovi, H. 1996. "Flow-through latch and edge-triggered flip-flop hybrid elements", IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp: 138-139.

[16.] Consoli, E., M. Alioto, G. Palumbo, J. Rabaey, 2012. "Conditional push -pull pulsed latch with 726 fJops energy delay product in 65 nm CMOS", IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp: 482-483.

(1) B. Gowthami, (2) C. Maheswari, (3) V. Navya

(1) Assistantprofessor, Sree vidyanikethan engineering college, Ttirupathi, A.P, lindia.

(2) Assistantprofessor, Sree vidyanikethan engineering college, Ttirupathi, A.P, lindia.

(3) Assistantprofessor, Sree vidyanikethan engineering college, Ttirupathi, A.P, lindia.

Received 28 March 2017; Accepted 7 June 2017; Available online 12 June 2017

Address For Correspondence:

B.Gowthami, Assistant professor, Sree vidyanikethan engineering college, ECE Department, Ttirupathi, A.P, Iindia, phone:918897071908; E-mail: ggowthamiece@gmail.com

Caption: Fig. 1: Design of Flip-flop using two latches and for the design of pulsed latch.

Caption: Fig. 2: Design model for generic Pulsed latch and Multi-bit pulsed latch.

Caption: Fig. 3: (a) The existing design of Pulsed clock signal. (b) The existing pulsed flip-flop design

Caption: Fig. 4: (a) Master Slave Flip Flop (b) Pulsed Latch

Caption: Fig. 5: Delayed Pulsed Clock Generator

Caption: Fig. 6: Static Differential Sense Amplifier Shared Pulse Latch (SSASPL)

Caption: Fig. 7: Power Pc-Style Flip Flop (PPCFF)

Caption: Fig. 8: Shift register with latches and a pulsed clock signal. (a) Schematic. (b) Waveforms.

Caption: Fig. 9: Shift register with latches, delay circuits, and a pulsed clock signal. (a) Schematic. (b) Waveforms.

Caption: Fig. 10: Shift register with latches and delayed pulsed clock signals. (a) Schematic. (b) Waveforms.

Caption: Fig. 11: Proposed Shift Register (a) Schematic (b) Waveforms

Caption: Fig. 12: Simulation Result of Master Slave Flip Flop

Caption: Fig. 13: Simulation Result of Pulsed Latch

Caption: Fig. 14: Simulation Result of SSASPL

Caption: Fig. 15: Simulation Result of PPCFF

Caption: Fig. 16: Simulation Result of Shift register with latches and a pulsed clock signal

Caption: Fig. 17: Simulation Result of Shift Register with latches, delay circuits and a pulsed clock signal

Caption: Fig. 18: Simulation Result of Shift Register with latches and Delayed pulsed clock signals

Caption: Fig. 19: Simulation Result of Proposed Shift Register
Table I: Comparison Of Master Slave Flip Flop And Pulsed Latch

Latch          Parameters Measured

               Delay    Power          Power     Area
               (nS)     Consumption    Delay     ([micro]
                        (mW)           Product   [m.sup.2])

Master Slave   8.1422   2.4662         34.8559   76
  D-FlipFlop
Pulsed latch   4.2809   2.6495         11.3422   44

Table II: Comparison of SSASPL and PPCFF Memory Elements

Latch    Parameters Measured

         Delay     Power         Power     Area
         (nS)      Consumption   Delay     ([micro]
                   (mW)          Product   [m.sup.2])
                                 (pW-S)

SSASPL   0.17703   20.441        3.6186    11
PPCFF    3.6596    0.14236       0.5209    32

Table III: Comparison Of 8-Bit Shift Register Combinations

Latch                 Parameters Measured

                      Delay     Power         Power     Area
                      (nS)      Consumption   Delay     ([micro]
                                (mW)          Product   [m.sup.2])

Shift register with   0.10007   2.6531        0.2655    116
  latches and a
  pulsed clock
  signal
Shift Register with   0.10602   2.6392        0.2798    132
  latches, delay
  circuits and a
  pulsed clock
  signal
Shift Register with   0.10743   2.6689        0.2867    132
  latches and
  Delayed pulsed
  clock signals
Proposed Shift        0.51950   0.32451       0.16858   360
  register
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Author:Gowthami, B.; Maheswari, C.; Navya, V.
Publication:Advances in Natural and Applied Sciences
Geographic Code:1USA
Date:Jun 1, 2017
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