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Design and implementation of an L-band PLL frequency synthesizer.

In 1932, De Bellescize published his synchronized detection theory and described the PLL for the first time. In 1947, a PLL design was first applied in synchronize scanning of a television receiver. During the 1970s, owing to the rapid development of semiconductor technology, IC component and single-chip PLLs were constructed. Currently, PLLs are used for many radio applications, including receiver modulators and demodulators, clock and data recovery circuits, and frequency synthesizers. In recent years, the market for wireless personal communication systems in the low gigahertz frequency range has blossomed. Specifically, the 1.8 GHz frequency band is a new commercial band for wireless local area network (WLAN) applications released from military operation.

A pure, stable, fast tunable source is an important requirement in wireless communication systems. As a result, a PLL that tracks phase differences between an input and the feedback signal as a frequency synthesizer is investigated. Three techniques have been developed[1,2] for designing frequency synthesizers: direct frequency synthesizer (DFS), indirect frequency synthesizer (IDFS) and direct digital frequency synthesizer (DDFS). A DFS has merits such as fine frequency resolution, low phase noise and fast frequency transfers. However, the device requires a large bulk size and high price and has the apparent shortcoming of generating unwanted spurious signals. A DDFS uses logic circuitry or a digital computer to convert a digital signal to an analog form. Although DDFS systems have some advantages (such as compact size, low power and fine frequency resolution with fast frequency switching), practical DDFS applications now are mostly applied in the tens of megahertz range and cannot fit the frequency requirements for mobile communications. Therefore, this article studies an IDFS that generates a stable, low phase noise, tunable signal source at low gigahertz frequencies.


The function of a PLL is to track phase differences between the input and feedback signals. The PLL, as shown in Figure 1, consists of a PD, loop filter and VCO. The phase comparator compares the phases of two signals. A digital phase/frequency (P/f) comparator that offers a wider operating range is used in the frequency synthesizer design.[2-4] The tri-state P/f comparator charge pump is constructed using two-D flip-flops for each operation. The charge pump converts the logic states of the P/f detector into analog signals for controlling the VCO.

A two-port negative-resistance oscillator, shown in Figure 2, is characterized by the oscillator transistor's S parameters, terminating network impedance [Z.sub.T] and load impedance [Z.sub.L]. When the transistor is in a potentially unstable state, an appropriate choice of [Z.sub.T] permits the two-port device to be represented as a one-port negative-resistance device with input impedance []. The conditions for a stable oscillation are

[absolute value of [](v, [Omega])] = [absolute value of [R.sub.L]([Omega])] (1)

[absolute value of [](v, [Omega])] = [absolute value of [X.sub.L]([Omega])] (2)

The final oscillation frequency [Omega] generally differs from the start-up frequency because [] is current (or voltage) dependent[5] so that [](v, [Omega]) [not equal to] []([v.sub.0], [[Omega].sub.0]). Thus, the conditions of Equation 2 will not ensure a stable state for oscillation. This condition occurs because the oscillation power increases until the negative resistance is equal to the load resistance. A feedback circuit sometimes is added to increase the negative resistance of the transistor associated with [[Gamma]] or [[Gamma].sub.out.] Kurokawa[6] has shown that a stable oscillation can be achieved if

[Mathematical Expression Omitted] (3)

In many cases,

[Delta][R.sub.L]/[Delta][Omega] = 0

(that is, [R.sub.L] is a constant) and[7]

[Delta][]/[Delta]V [greater than] 0

Equation 3 is satisfied if

[Delta][X.sub.L]/[Delta][Omega] [greater than] 0

which implies that the oscillation will be stable if the imaginary part of the circuit impedance has a positive slope with respect to the frequency.[8,9] The input and output ports are oscillating simultaneously when

[[Gamma]][[Gamma].sub.L] = 1 and [[Gamma].sub.out][[Gamma].sub.T] = 1 (4)

If [absolute value of [[Gamma]]] [greater than] 1, the real part of [] = [] + j[] becomes negative. As the oscillation power increases, the negative resistance of [] will decrease to the value of the load resistance at which point oscillation stops. Therefore, load impedance is selected such that [R.sub.L] = -[]/3 and [X.sub.L] = [].

The loop filter in a PLL system is an important component that links the VCO and PD. Since the PD and VCO designs are usually less flexible, the design of the loop filter becomes the principle tool with which to determine a PLUs bandwidth. Compared to an active filter, a passive filter is desirable for its simplicity, low cost and phase noise performance.[10, 11] Figure 3 shows the passive loop filter with its transfer function. Figures 4 and 5 show the passive loop filter's frequency response and open-loop gain, respectively. The passive loop filter has a pole at the origin that enables the attenuation slope to reach -12 dB/octave to reduce the PLL bandwidth. The filter's zero changes the attenuation slope from -12 dB/octave to 6 dB/octave, crossing the 0 dB gain at PLL bandwidth K. The Bode theorem implies that the system is stable. The PLL bandwidth K can be changed to reduce the noise by choosing the angular frequency [[Omega].sub.2]. Therefore, this method proves to be very important and effective in reducing the PLL noise at the cost of decreasing the PLUs bandwidth.[2]

Although the PLL circuit is nonlinear due to the character of the PD, it still can be modeled as a linear device when the loop is in lock, as shown in Figure 6.[12] When the loop is locked, it is assumed that the PD output voltage is proportional to the phase difference between its inputs such that

[v.sub.d] = [[Kappa].sub.d]([[Theta].sub.i] - [[Theta].sub.o]/N) (5)


[[Theta].sub.i] = phase at the input

[[Theta].sub.o] = phase at the VCO's output

[[Kappa].sub.d] = PD gain factor

It is assumed that the VCO is modeled as a linear device whose output frequency deviates from its free-running frequency by an increment of frequency[12] such that

[Mathematical Expression Omitted] (6)


[v.sub.c] = voltage at the output of the lowpass filter

[[Kappa].sub.o] = VCO gain factor

Since frequency is the time derivative of phase, the VCO operation can be described as

[Mathematical Expression Omitted] (7)

The result in the frequency domain using the Laplace transformation is

[[Theta].sub.o](s) = [[Kappa].sub.o][v.sub.c](s)/s (8)

The VCO's model now includes an integrator to provide the phase [[Theta].sub.o] as the PLL's output. Using these assumptions, the PLL's linear model is shown with feedback. The transfer functions are

forward-loop gain = G(s)

= [K.sub.d]F(s)[K.sub.o]/s

reverse-loop gain = H(s)

= 1/N

open-loop gain = [T.sub.o](s)

= [[Theta].sub.o]/[[Theta].sub.e]

= G(s)H(s)

= [K.sub.d]F(s)[K.sub.o]/Ns

closed-loop gain = [T.sub.c](s)

= [[Theta].sub.o]/[[Theta].sub.i]

= G(s)H(s)/1 + G(s)H(s)


[K.sub.d] = PD/charge pump constant

[K.sub.o] = VCO tuning voltage constant

F(s) = loop filter transfer function

N = frequency divider ratio

[[Theta].sub.e] = represents the phase error between the incoming reference signal [[Theta].sub.i] and the feedback [[Theta].sub.o]/N. [[Theta].sub.e] should be determined carefully and the steady-state evaluation can be simplified using the final value of the Laplace transformation[13]

[Mathematical Expression Omitted] (9)


[[Theta].sub.e](s) = 1/1 + G(s)H(s) [multiplied by] [[Theta].sub.i](s) (10)

in phase form,

[[Theta].sub.i](t) = [f.sub.0] t (11)

in Laplace notation,

[[Theta].sub.i](s) = [f.sub.0]/[s.sup.2] (12)

The final value of the phase error with a step velocity input is determined using Equations 9 and 10.

[Mathematical Expression Omitted] (13)

The frequency error

[f.sub.e](t) = d/dt[[Theta].sub.e](t)

is zero when it is at the steady state. If it is assumed that the phase error of the system is zero, [Mathematical Expression Omitted] must be an infinite value. In the circuit's design consideration, this condition is attainable through a loop filter pole at the origin. This pole may influence the loop stability unless a lead network in F(s) is added. Applying the Bode diagram is an easy way to forecast the loop stability by analyzing the open-loop gain. Figure 7 and Equations 14 and 15 show the stability regions of open-loop stability with the considerations on gain and phase margins.[2]

20log [absolute value of [T.sub.o](j[[Omega].sub.k])] [less than] 0 dB [absolute value of [Theta]([[Omega].sub.k])] = [Pi] (14)

20log [absolute value of [T.sub.o](j[[Omega].sub.c])] = 0 db [absolute value of [Theta]([[Omega].sub.c])] [less than] [Pi] (15)


The main components in the L-band PLL include an FR-4 substrate with relative permittivity [[Epsilon].sub.r] = 4.75 and, thickness H = 31 mil, a Hitachi HVU12 varactor diode with maximum and minimum capacitances of 5.6 to 0.45 pF, an NEC 2SC3603 npn bipolar-junction transistor with low noise characteristics for the VCO's active device and a National LMX2330 IC for the PLL. An HP8563E spectrum analyzer and HP5350B frequency counter were used for experimental measurements of the designed VCO and PLL circuits.

A clocked data stream programs the National LMX2330 IC,[14] which contains dual modulus prescalers (32/33 or 64/65), a selectable reference divider and a digital PD (charge pump tri-state). The device has a seven-bit programmable divide-by-A counter, 11-bit programmable divide-by-B counter and the necessary shift register with latch circuitry for serial input data. The division ratio of the PLUs swallow counter is controlled by two inputs. The counter is divided by 64 when either input is in the high state and by 65 when both inputs are in the low state. If the number loaded into A is greater than zero, the prescaler is set to divide by 64 + 1. When A is full, the prescaler ceases counting and sets the divider into the divide-by-64 mode. When B is full, the prescaler resets both A and B and the cycle restarts.

[] = (64 + 1)A + 64(B - A)

= 64B + A (16)

When the loop is locked, the output frequency is equal to N-times the reference frequency,

[f.sub.VCO] = [] [multiplied by] [f.sub.step]

= (64B + A) [multiplied by] [f.sub.step] (17)

It is common knowledge that the channel spacing in the GSM1800 system is 200 kHz. Therefore, when a 12 MHz crystal oscillator is applied as the reference frequency, the reference divider is

[f.sub.step] = 12 MHz/60

= 200 kHz (18)

The PLL control signal (serial data) comprises three inputs: a data pin, clock pin and enable pin. Serial data input controls the 15-bit programmable reference divider (R counter) and 18-bit programmable divider (N counter), respectively. The N counter consist of a seven-bit swallow counter (A counter) and an 1 i-bit programmable counter (B counter). The data stream is clocked (on the rising edge of enable) into the DATA input. A Turbo C program was written to control the signals of the R and N counter outputs from a PC's printer port for determining the PLL's channel frequency in mobile communications applications.

The VCO transistor's configuration is designed to be in a potentially unstable state at the desired frequencies. Feedback is added to increase the negative resistance associated with [[Gamma]] or [[Gamma].sub.out], as shown previously.[15] A schematic diagram of the designed VCO, as shown in Figure 8, uses series feedback to realize the negative resistance with a matching network on the collector. HP EEsof Libra software is applied for simulations and the slope of the load reactive component is verified to satisfy the condition of [Delta][X.sub.L]/[[Delta].sub.[Omega]] [greater than] 0 from 1.8 to 2 GHz. Figure 9 shows the result of the designed VCO with good tuning linearity of approximately 38 MHz/V from 1.81 to 1.96 GHz and less than -104 dBc/Hz phase noise at 100 kHz offset from the carrier frequency.

One of the main performances of the PLL is determined by the loop filter, which decides the loop stability, phase noise, loop response time and reference frequency attenuation. The passive loop filter (shown previously) uses a shunt capacitor C1 to avoid discrete voltage steps due to the instantaneous changes in the charge pump current output. In wireless communications, the PD for frequency comparison generally is used in multiple channel spacing applications. Since the sidebands' spurious effects may cause noise in adjacent channels, how narrow the loop filter is determines how well the reference spurs are screened out. For these requirements, a series resistor R3 and a shunt capacitor C3 have been added to the loop filter design,[16] as shown in Figure 10. This loop filter is placed prior to the VCO circuit of the designed PLL to provide a lowpass pole for additional attenuation at the unwanted spurs. Figure 11 shows the magnitude of the open-loop gain by adding [[Omega].sub.3] in the PLL system.


C1 (pF)                  1000
R2 (k[Omega])             3.9
C2 ([[micro]farad])      0.01
R3 (k[Omega])              15
C3 (pF)                   100

The loop filter should be designed for the correct balance between reference spur attenuation and lock time that the system requires. The narrower the loop bandwidth, the lower the reference spurs and the longer the lock time. A program was designed using Matlab to determine the component values of the loop filter. The Bode diagram method is applied to judge the stability of the loop. A common rule of thumb is to begin the design with a 45 [degrees] phase margin at 0 dB gain margin. VCO output frequencies from 1800 to 1950 MHz and possible tuning sensitivity from 30 to 50 MHz/V are used for simulation. The element values of C1, C2, R2, C3 and R3 are calculated a thousand times or more to match the stability and bandwidth requirements. In addition, the optimum element values for phase margin farthest from [Pi] of an open-loop function in favor of stability requirement are listed in Table 1.

Appendix A shows the completely designed PLL circuit. Compared to the designed VCO, the phase noise of the designed synthesizer is improved by approximately 5 to 6 dBc/Hz. The experiment confirms that the L-band frequency synthesizer generates stable, low phase noise and controllable locked signals at the desired channel frequencies in a GSM1800 mobile system.


The design methodology, fabrication and measurement of an L-band PLL frequency synthesizer have been described. Libra software was utilized for circuit simulation and a program was written using Matlab to calculate the phase and gain margins of an open-loop circuit and to verify the stability of the closed-loop circuit. Optimal values in the loop filter also were determined using this program.

Based on these simulations, the L-band synthesizer was designed and fabricated. A designed VCO furnished good tuning linearity of 38 MHz/V at L-band and less than -104 dBc/Hz phase noise at 100 kHz offset from the carrier frequency was obtained. Experimental results show that the designed PLUs phase noise is better than the VCO's by approximately 5 to 6 dBc/Hz. The resulting data proved the designed frequency synthesizer generates stable, low phase noise and controllable locked signals at the desired channel frequencies in mobile communications.


The authors wish to express their sincere thanks to Microelectronics Technology Inc. (Science-based Industrial Park, Hsinchu, Taiwan) for its assistance.


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5. D.M. Pozar, Microwave Engineering, Addison-Wesley, 1990.

6. K. Kurokawa, "Some Basic Characteristics of Broadband Negative Resistance Oscillator Circuits," The Bell System Technical Journal, July 1969.

7. Guillermo Gonzalez, Microwave Transistor Amplifiers Analysis and Design, Second Edition, Prentice Hall, 1997.

8. David A. Warren, J. Michael Golio and Warren L. Seely, "Large and Small Signal Oscillator Analysis," Microwave Journal, Vol. 32, No. 5, May 1989, pp. 229-246.

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11. David Byrd, Craig Davis and William O. Keese, A Fast Locking Scheme for PLL Frequency Synthesizers, National Semiconductor Application Note AN-101, July 1995.

12. Dan H. Wolaver, Phase-locked Loop Circuit Design, Prentice Hall, Englewood Cliffs, NJ, 1991.

13. Garth Nash, Phase-locked Loop Design Fundamentals, Motorola Application Note AN-535, July 1995.

14. National PLL IC Data Book.

15. John Kitchen, "Octave Bandwidth Varactor-tuned Oscillators," Microwave Journal, Vol. 30, No. 5, May 1987, pp. 347-353.

16. William O. Keese, An Analysis and Performance Evaluation of a Passive Filter Design Technique for Charge-pump Phase-locked Loop, National Semiconductor Application Note AN-1001, May 1996.
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Author:Sun, Jwo-Shiun; Tiong, Kwong-Kau; Liu, Jiann-Hwang
Publication:Microwave Journal
Geographic Code:1USA
Date:Apr 1, 1999
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