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Design a full adder based GDI logic using FinFET technology.


Due to technology development, the need for low power, high speed and more packing density of integrated chips (ICs), the scaling of devices became inevitable. However, the scaling of CMOS technology reaches its limit due to the short channel effects. Multi-gate MOSFET or FinFET happens to be better replacement for CMOS for scaling beyond sub-micron regime [1]. The double-gate (DG) FinFET [3] is of most interest because of its excellent suppression of short-channel effects (SCEs) and its relatively easy fabrication and integration [2]. Due to novel device structure, FinFET technology provides less static power consumption [3]. Nowadays, building low-power VLSI systems has emerged as highly in demand because of the fast growing technologies in mobile communication and computation.

The battery technology doesn't expand at the same rate as the microelectronics technology. There is a restricted amount of power available for the mobile systems. So, designers are faced with more limitations: high speed, high throughput, small silicon area, and at the same time, low-power consumption. Therefore, building low-power, high-performance adder cells is of great interest [4].

In recent years, various logic styles have been proposed to implement low power adder. The aim of the paper is to implement the full adder to reduce power and delay. The main idea behind this paper aims at design, analysis and improvement of power efficiency. The aspect for improving the performance of circuits based on CMOS logic resulted in introduction of many logic styles like Pass Transistor logic (PTL), Transmission Gate logic (TG), Double Pass Transistor logic (DPTL) and also many other hybrid logics.

One of the most widely used logics for low power digital circuit is Pass Transistor Logic. It has many advantages over CMOS, i.e. high speed, low power dissipation and lower interconnection effects. GDI Technique can trounce certain drawbacks of PTL Logic. A wide range of complex logic functions in which PTL was used, can be replaced by GDI Technique and this makes the circuit simple [4-6].

Gate Diffusion Input (GDI) is a lowest power design technique which offers improved logic swing and less static power dissipation. This method is suitable for design of fast, low-power circuits, using a reduced number of transistors [5].

The paper is structured as follows: Section 2 overviews the GDI methodology. The three proposed full adders implementations based on FinFET are discussed in section 3. Section 4 discusses the simulation results of GDI based full adder designs in terms of Power, Delay and Power-Delay Product (PDP). The conclusion is drawn in Section 5.

GDI Logic:

The basic GDI cell is shown in below Fig.1. Though it resembles a conventional CMOS inverter the source/drain diffusion input of both PMOS and NMOS transistor is different. Source and drain diffusion input of PMOS and NMOS transistors are always coupled at VDD and GND potential in conventional inverter circuit. On the other hand, the diffusion terminal acts as an external input in the GDI cell [5-9].

It helps in the realization of various Boolean functions such as AND, OR, MUX, INVERTER, F1 and F2, as listed in Table 1. This is achieved by a change of the input configuration of the GDI cell. The Multiplexer (MUX) is the most complex function that can be implemented with a basic GDI cell, while being the most efficient function as compared to CMOS implementation.

GDI logic cell consists of four terminals. They are

* G (Common Gate input of NMOS and PMOS transistor),

* P (Outer diffusion node of PMOS transistor),

* N (Outer diffusion node of NMOS transistor),

* Out (Common diffusion node of both transistors)

Table I, shows how a simple change of the input configuration of the simple GDI cell corresponds to very different Boolean functions. In this paper, most of the designed circuits were based on the F1 and F2 functions. The reasons for this are as follows.

1) Both F1 and F2 are complete logic families.

2) F1 is the only GDI function that can be realized in a standard p-well CMOS process, because the bulk of any NMOS is constantly and equally biased.

3) While N input is taken at high logic level and P input is at low logic level, the diodes between NMOS and PMOS bulks to Out are directly polarized and there is a short between N and P, resulting in static power dissipation.

Full adder design:

The logic function of basic full adder can be represented as

Sum = A XOR B XOR [] (1)

[C.sub.out] = A AND B + B AND [] + A AND [] (2)

Eqs. (1) and (2) are accommodate the full swing gates. By, rewriting the above full adder designs expression, the following three possible full swing GDI full adders are designed. The proposed first full adder's (Design 1) Sum and [C.sub.out] expressions are given in Eqs. (3) and (4), respectively.

Sum = [] (A XOR B) + [] (A XNOR B) (3)

[C.sub.out] = (A XOR B) [] + (A XOR B) A (4)

Design 1 uses XOR output as an intermediate result. [C.sub.out] is attained by multiplexing the inputs A and [] whose output is controlled by the selection input. Sum output can be achieved by multiplexing the XOR and its inverted version XNOR through [] input.

The presence of inverter on the critical path increases the delay of the entire circuit. This design is simple and requires a total of 18 transistors for realizing the full adder function. The resultant output waveform of Full adder Design 1 is given below and it is verified by truth table of the above design.

Design 2 The Sum and [C.sub.out] expressions are represented in Eqs. 5 and 6, respectively.

Sum = A XOR B XOR [] (5)

[C.sub.out] = [] (A AND B) + [] (A OR B) (6)

The XOR operation on the inputs A, B and [] achieves Sum function. [C.sub.out] function can be accomplished with the help of AND and OR gates. AND and OR gates are designed based on F1 and F2, respectively. Multiplexing the AND and OR operation through Carry input [] helps in [C.sub.out] realization. It requires total 28 transistors.

The resultant output waveform of Full adder Design 2 is given below and it is verified by truth table of the above design

Design 3 It is designed by considering the XOR, AND and OR gates and the Sum and [C.sub.out] design expressions are given in Eqs. (7) and (8).

Sum = A XOR B XOR [] (7)

[C.sub.out] = A AND B + (A XOR B) [] (8)

Sum output can be achieved by XORing the inputs A, B and []. The output [C.sub.out] is obtained with the help of AND and OR tracked by XOR gate. The realization of AND and OR gate can be done with the help of full swing F1 and F2 gates. So totally, 27 transistors are needed for designing a full adder. The proposed full adder based on Design 1, Design 2 and Design 3 are shown in the Fig 2, 4, 6.

The resultant output waveform of Full adder Design 3 is given below and it is verified by truth table of the above design.

Result analysis:

Table II. shows the variation of average power and delay of proposed GDI based full adder design. Three GDI full adders are designed based on the full swing AND, OR and XOR gates discussed in previous section and results are compared with existing work under CMOS 32 nm technology.

* Design 1 is a best possible candidate for the applications in which minimum transistor count and low power is a design requirement.

* Design 2 offers minimum delay, so it can be suitable for battery operated and real-time applications. It has increased in transistor count compared with design 1.

* Design 3 offers lower delay than design 1 and it lies midway between design 1 and design 2.

From the obtained results, it can be concluded that all the three proposed designs using FinFET operate with less power consumption than existing adders taken for comparison using CMOS. Hence, these designs can be suitable for realizing energy efficient arithmetic applications.


In this work, three full adder designs that use as few as thirty transistors per bit are proposed. The design adopts full swing XOR, AND and OR gates to reduce the threshold voltage problem and to enhance the driving capability for cascaded operation. The enhanced driving capability also assists lower voltage and faster operation which leads to less power dissipation. The proposed designs are simulated using the SPICE simulation tool at 32 nm FinFET technology. The comparison is done in terms of power consumption, propagation delay and Power-Delay Product. Hence, these proposed designs may be suitable for low power and delay VLSI circuit applications.


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(1) V.M. Senthilkumar, (2) K.Stella

(1) Associate Professor, Dept of ECE Vivekanandha College of Engineering for Women Tiruchengode, Tamiinadu, India

(2) PG Student, VLSI Design, Dept of ECE Vivekanandha College of Engineering for Women Tiruchengode, Tamiinadu, India

Received 28 January 2017; Accepted 22 March 2017; Available online 28 April 2017

Address For Correspondence:

V. M. Senthilkumar, Associate Professor, Dept of ECE Vivekanandha College of Engineering for Women Tiruchengode, Tamilnadu, India

E-mail: vmspraneeth

Caption: Fig. 1: GDI basic cell.

Caption: Fig. 2: Design 1 Full adder.

Caption: Fig. 3: Output waveform Design 1.

Caption: Fig. 4: Design 2 Full adder.

Caption: Fig. 5: Output waveform Design 2.

Caption: Fig. 6: Design 3 Full adder.

Caption: Fig. 6: Output waveform Design 3.
Table I: Various logic functions of GDI cell for different input

N   P   G    Out     Function
0   B   A    A'B        F1
B   1   A    A'+B       F2
1   B   A    A+B        OR
B   0   A     AB       AND
C   B   A   A'B+AC     MUX
0   1   A     A'       NOT

Table II: Comparison of Full adders.

FULL                  CMOS 32 nm
           Power (mW)   Delay (ps)      PDP

Design 1     0.706        991.6      8.17 E-15
Design 2      1.05        990.68     5.60 E-15
Design 3     0.810        999.99     6.65 E-15

FULL                FinFET 32 nm
             Power      Delay      PDP
           ([micro]W)   (ns)

Design 1     0.373        5     1.84 E-15
Design 2     0.407      4.86    1.98 E-15
Design 3     0.406      4.98    2.02 E-15
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Author:Senthilkumar, V.M.; Stella, K.
Publication:Advances in Natural and Applied Sciences
Article Type:Report
Date:Apr 30, 2017
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