# Design a FinFET based 4-2 compressor for arithmetic operation.

INTRODUCTIONToday mobile and computing markets continue to innovate at a dramatic rate delivering more performance in smaller form factors with higher power efficiencies. According to Moore's law, the number of transistors in an area should double every months. To make this into reality, transistors should get shrink in size to accommodate double the number per unit area. While scaling down the device channel length, the short channel effects are raised. As the technology scaling continues, FinFET is known to be a probable alternative to solve the problems related to short channel effects of planar technology. In a DG device, the channel is surrounded by two gates on surfaces, allowing more effective suppression of "off-state" leakage current. DG gates also allow enhanced current in the "on" state, also known as drive current. These advantages translate to lower power consumption and enhanced device performance.

The main advantage is that better control of short channel effects, lower leakages and better yield in aggressively scaled CMOS process, will require overcoming these obstacles to scaling..Double gate MOSFETs (DG-FET) is a MOSFET that has two gates to control the channel. Its main advantage is that of improved short channel effects. Now a day FinFET is usually using because of short channel effects, better in driving current, more compactable that other device. FinFETs are substitutes for bulk CMOS. The two gates for FinFETs provide effective control of the short-channel effects without aggressively scaling down the gate-oxide thickness and increasing the channel doping density. The separate biasing in DG device easily provides multiple threshold voltages.

Proposed compressor:

A. Design 1:

In Design 1, the carry is simplified to cm by changing the value of the other 8 outputs.

Carry' = [C.sub.in] (1)

Sum' = [c.sub.in'] ((x1 x2)' + (x3 x4)') (2)

[c.sub.out'] = ((x1 x2)' + (x3 x4)') (3)

Table 1 shows the truth table of the first proposed approximate compressor. The proposed design 1 has 12 incorrect outputs out of 32 outputs thus yielding an error rate of 37.5%. This is less than the error rate using the best approximate full-adder cell of [2].

Eqs (1)-(3) are the logic expressions for the outputs of the first design of the approximate 4-2 compressor proposed in this manuscript. The gate level structure of the first proposed design shows that the critical path of this compressor has still a delay of 3A, so it is the same as for the exact compressor. However, the propagation delay through the gates of this design is lower than the one for the exact compressor. Therefore, the critical path delay in the proposed design is lower than in the exact design and moreover, the total number of gates in the proposed design is significantly less than exact compressor.

B. Design 2:

A second design of an approximate compressor is proposed to further increase performance as well as reducing the error rate. In this new design, carry uses the right hand side of eqn (3) and [c.sub.out] is always equal to [c.sub.in]; so, [c.sub.in] and [c.sub.out] can be ignored in the hardware design. Table 2 shows the truth table of the first proposed

approximate compressor.

Sum' = ((x1 x2)' + (x3 x4)') (4)

Carry' = ((x1 x2)' + (x3 x4)')' (5)

The proposed design 2 has 4 incorrect outputs out of 16 outputs thus yielding an error rate of 25%.The critical path delay of this approximate design is 2[DELTA], so it is 1[DELTA] less than the previous designs; moreover, a further reduction in the number of gates is accomplished.

4x4 Dadda multiplier:

DADDA multiplier is extracted form of parallel multiplier [5]. It is slightly faster and requires fewer gates. Different types of schemes are used in parallel multiplier. The DADDA scheme is one of the parallel multiplier schemes that essentially minimize the number of adder stages required to perform the summation of partial products. This is achieved by using full and half adders to reduce the number of rows in the matrix number of bits at each summation stage. Even though the DADDA multiplication has regular and less complex structure, the process is slower in manner due to serial multiplication process. Further, DADDA multiplier is less expensive compared to that of Wallace tree multiplier.

A. Algorithm of dadda multiplier:

Steps involved in DADDA multipliers Algorithm:

1) Multiply (that is--AND) each bit of one of the arguments, by each bit of the other, yielding N results. Depending on position of the multiplied bits, the wires carry different weights.

2) Reduce the number of partial products is achieved by using FinFET based compressor and full adders.

3) In the last part a FinFET based conventional adder is used to compute the final binary results as shown in Fig.3.

B. Conventional dadda multiplier:

In this design, only full and half adders are used.The partial product matrix is formed in the first stage by AND gates. Reduce the number of partial products to two layers of full adders. For the final computation of the binary result, full adder is used as shown in Fig 4. But power consumption is higher.

C. Dadda multiplier using 4-2 compressor:

The partial product matrix is formed in the first stage by AND gates. In this design, compressor and conventional adders are used to reduce the partial product stage. For the final computation of the binary result, full adder is used as shown in Fig.5. But power consumption is lower than conventional Dadda.

D. Proposed dadda multiplier:

The partial product matrix is formed in the first stage by AND gates. In this design, FinFET based 4-2 compressor and full adders are used to reduce the partial product stage. Proposed full adder is designed using only 10 transistors and it is used in final computation of the binary result as shown in Fig 6. Power consumption and delay is lower compared to other Dadda designs.

Consider the 4 bit multiplicand and multiplier as 0. The average delay generated by this Dadda multiplier is shown in Fig.7.

Result analysis:

The above Table 3 shows that proposed FinFET based Dadda multiplier are better than the other multipliers.

Conclusion:

In this paper, different 4X4 Dadda multipliers are proposed. The multiplier design utilized the proposed 4-2 compressor and full adder using 10 transistors. The proposed designs are simulated using the HSPICE simulation tool at 32 nm FinFET technology. The comparison is done in terms of power consumption, propagation delay and Power-Delay Product (PDP). Hence, these proposed designs will be suitable for image processing applications.

REFERENCES

[1.] Chang, C., J. Gu, M. Zhang, 2004. "Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits," IEEE Transactions on Circuits & Systems, 51(10): 1985-1997.

[2.] Cheemalavagu, S., P. Korkmaz, K.V. Palem, B.E.S. Akgul, and L.N, 2005. "A probabilistic CMOS switch and its realization by exploiting noise," in Proc. SOC, Perth, Western Australia.

[3.] Gu, J., C. H. Chang, 2003. "Ultra low-voltage, low-power 4-2 compressor for high speed multiplications', in Proc. 36th IEEE Int. Symp. Circuits Systems, Bangkok, Thailand.

[4.] Gupta, V., D. Mohapatra, S.P. Park, A. Raghunathan, K. Roy, 2011. "IMPACT: Imprecise adders for low-power Approximate Computing," Low Power Electronics and Design (ISLPED) International Symposium on, pp: 1-3.

[5.] King, E.J. and E. E. Swartzlander, Jr., 1998. "Data dependent truncated scheme for parallel multiplication,' in Proceedings of the Thirty First Alomar Conference on Signals and Systems, pp: 1178-1182.

[6.] Kulkarni, P., P. Gupta and S. Ercegovac, 2011. "Trading accuracy for power in a multiplier architecture," Journal of Low Power Electronics, 7(4): 490-501.

[7.] Liang, J., J. Handan, F. Lombardi, 2013. "New metrics for the reliability of approximate and probabilistic adders', IEEE Transactions on Computers, 63(9): 1760-1771.

[8.] Mahanadi, H.R., A. Hamada, S.M. Fakhraie and C. Lucas, 2010. "Bio-inspired imprecise computational blocks for efficient VLSI implementation of soft-computing applications," IEEE Transactions on Circuits and Systems I: Regular Papers, 57(4): 850-862.

[9.] Margala, M. and N.G. Durdle, 1999. "Low-power low-voltage 4-2 compressors for VLSI applications," in Proc. IEEE Alessandro volta memorial workshop low-power design, pp: 84-90.

[10.] Mustafa, K., G. Vojin and S. Oklobdzi, 2010. " Energy efficient implementation of parallel CMOS multipliers with improved compressors. 'Proc. Of the 16th ACM/IEEE International Symposium on Low power electronics and design.

[11.] Parhami, B., 2010. "Computer arithmetic: algorithms and hardware designs," 2nd edition, Oxford University Press, New York.

[12.] Prasad, K. and K. Parham, 2001. "Low-power 4-2 and 5-2 compressors," in Proc. of the 35th Alomar on Signals, Systems and Computers, 1: 129-133.

[13.] Radhakrishnan, D. and A.P. Pretty, 2000. "Low-power CMOS pass logic 4-2 compressor for high-speed multiplication, "in Proc. 43rd IEEE Midwest Symp. Circuits Syst., 3: 1296-1298.

(1) V.M. Senthilkumar, (2) S. Sowmiya

(1) Associate Professor, Dept of ECE Vivekanandha College of Engineering for Women Tiruchengode, Tamiinadu, India

(2) PG Student, VLSI Design, Dept of ECE Vivekanandha College of Engineering for Women Tiruchengode, Tamiinadu, India

Received 28 January 2017; Accepted 22 March 2017; Available online 28 April 2017

Address For Correspondence:

V.M. Senthilkumar, Associate Professor, Dept of ECE Vivekanandha College of Engineering for Women Tiruchengode, Tamilnadu, India

E-mail: vmspraneeth@gmail.com

Caption: Fig. 1: Implementation of 4-2 compressor.

Caption: Fig. 2: 4-2 compressor: Design 2.

Caption: Fig. 3: 4x4 DADDA Algorithm.

Caption: Fig. 4: Schematic view of conventional Dadda.

Caption: Fig. 5: Schematic view of FinFET based Dadda multiplier using 4-2 compressor.

Caption: Fig. 6: Schematic view of proposed FinFET based Dadda multiplier.

Caption: Fig. 7: Delay waveform of proposed FinFET based Dadda multiplier.

Table 1: Truth table of design 1 compressor. Cin X4 X3 X2 X1 Cout' Carry' Sum' 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 1 1 0 0 0 0 1 1 0 1 0 0 0 0 1 1 1 1 0 1 0 1 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 0 1 0 1 0 0 0 1 0 1 1 1 0 1 0 1 1 0 0 0 0 1 0 1 1 0 1 1 0 1 0 1 1 1 0 1 0 1 0 1 1 1 1 1 0 1 1 0 0 0 0 0 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 0 1 0 1 0 0 1 1 0 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1 1 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 1 1 0 0 0 0 1 0 1 1 0 0 1 1 1 0 1 1 0 1 0 1 1 0 1 1 0 1 1 1 1 0 1 1 1 0 0 0 1 0 1 1 1 0 1 1 1 0 1 1 1 1 0 1 1 0 1 1 1 1 1 1 1 0 Table 2: Truth Table of Design 2. X4 X3 X2 X1 Carry' Sum' 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 0 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 0 1 0 0 1 1 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 0 0 0 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 Table 3: Comparison of Dadda Multiplier DADDA CMOS 32 nm MULTIPLIER Power (mw) Delay PDP (mw) Conventional 3.66 1.25 1.21 E-03 Design 1 5.82 9.56 5.27 E-11 Design 2 5.81 2.88 4.68 E-ll Design 3 7.87 1.99 1.50 E-ll DADDA FinFET 32 nm MULTIPLIER Power (mw) Delay PDF (mw) Conventional 0.527 1.16 2.50 E-11 Design 1 O.345 0.934 3.22 E-13 Design 2 0.345 0.934 3.02 E-13 Design 3 0.227 0.930 2.16S E-13

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Author: | Senthilkumar, V.M.; Sowmiya, S. |
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Publication: | Advances in Natural and Applied Sciences |

Article Type: | Report |

Date: | Apr 30, 2017 |

Words: | 2070 |

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