Design Options for Current Limit and Power Limit Circuit Protections for LDOs.
A low drop-out voltage regulator (LDO) dissipates surplus power as heat and this could cause excessive temperature rise on the power stage, [T.sub.PASS]. To prevent destructive effects the die temperature should be maintained bellow a safe threshold  by limiting the product of the output current by the voltage drop across the pass transistor ([P.sub.Tpass] = [V.sub.DROP]*[I.sub.Qlimit], where [V.sub.DROP]=VIN-VQ).
Short-circuits or overload situations are typical fault conditions for electronic devices [2-3]. In these scenarios the accuracy of the protection circuits is essential for the reliability and the robustness of the LDOs [4-5]. The simplest protection circuit to maintain the power dissipated bellow a set maximum value is the current limit protection [6-11]. The current limit circuitry sets the maximum value the output current can take, called here [I.sub.Qlimit], thus indirectly confining the maximum power dissipated by [T.sub.PASS]. A typical current limit implementation is shown in Fig. 1: a fraction of the output current IQ is sourced into a resistor and the resulting voltage is compared against a voltage reference; in Fig. 1 these voltages are denoted [V.sub.SENSE] and [V.sub.REF], respectively. When [V.sub.SENSE] gets larger than [V.sub.REF] the current limit circuit is activated, that is, the NPN transistor driven by the comparator turns off, sinking the current [I.sub.CLOUT] from the Error Amplifier (EA); thus, the main feedback loop implemented by the EA is broken. Instead, a new negative feedback loop is established by the current limit circuit and transistors [T.sub.DRIVER], [T.sub.PASS] and [T.sub.SENSE] that ensures the equality between [V.sub.SENSE] and [V.sub.REF] by controlling the output current - effectively setting its value to [I.sub.Qlimit].
When the output is shorted to ground the [V.sub.DROP] reaches its worst-case (maximum) value leading also to the maximum value of the [P.sub.Tpass]. Important temperature gradients can appear across the power stage, leading to hotspots (locations where the die temperature peaks) which could increase even more the [I.sub.Qlimit]. If the current limit circuit has a large and positive temperature coefficient this could result in increasing the [I.sub.Qlimit] value, thus larger [P.sub.Tpass] and increasingly larger die temperature and the eventual chip destruction.
The fold-back current limit approach is a better choice for a large input voltage domain since this type of protection, once activated, reduces the values of both the output voltage (VQ) and current, [I.sub.Qlimit], therefore reducing [P.sub.Tpass]. However, the fold-back current limiting has to deal with latch-up issues after an overload condition [12-14].
Another important aspect is the [I.sub.Qlimit] variation with temperature; the standard solution is to implement a complementary to absolute temperature (CTAT) characteristic for [I.sub.Qlimit], as shown in Fig. 2 . But this results in a larger power being dissipated at lower temperatures and a possible destruction mechanism of the device . One potential solution is to implement an architecture that employs a temperature calibrated current limit protection as presented in . But this approach results in complex structures that require large die area and quiescent current. Even so, this will not guarantee the robustness of the IC if the inherently un-even temperature distribution across the LDO is not taken into consideration and hot-spots are not controlled.
For a robust design one must ensure that all devices, [T.sub.PASS] in particular, stay within their safe operating area (SOA) for all operating scenarios, including predictable improper usage . The SOA of a power device is outlined by three electrical parameters: current, voltage and power . Therefore, limiting the current is not always sufficient to avoid the destruction region; in some cases, it is also necessary to control the dissipated power of the IC. For an LDO the factor [V.sub.DROP] is largely outside designer's control but it can be monitored and the [I.sub.Qlimit] can be dynamically optimized accordingly to limit the power dissipated.
The paper is organized as follows: Section II starts with a brief analysis of the low-power current limit implementation reported in ; next, an improved solution is presented, that significantly reduces the variation of the value the output current is limited to, caused by setting the output voltage to different values. Section III present two circuit solutions for ensuring that [T.sub.PASS] operates within its SOA; they are based on the current limit circuit proposed in Section II, but its activation point is made proportional to the sum of IQ and a current proportional to the voltage [V.sub.DROP]. A novel power limit circuitry for LDOs is presented in Section IV; it also employs the proposed current limit circuit but this time the activation point is proportional to the product of IQ and [V.sub.DROP]. Three LDOs that employ the three types of protections discussed here are compared in Section V. Section VI presents a summary and the main conclusions drawn from this work.
II. CURRENT LIMIT CIRCUITRY
A. Analysis of existing solutions
Most of the published current limit architectures occupy large die area and consume fairly large quiescent current [6-13]. The current limit circuitry proposed in  (shown in Fig. 3) overcomes these drawbacks: the circuitry is biased only by the sensed branch ([I.sub.SENSE]) and the area occupied is quite small. For the circuit shown in Fig. 13 the current limit circuit takes in [I.sub.SENSE] and the trip point value, ICLtrip, is temperature independent:
[mathematical expression not reproducible] (1)
The [I.sub.Qlimit] is obtained by multiplying the trip point, ICLtrip, with the current gain of [T.sub.PASS]-[T.sub.SENSE] mirror, considering not only the ratio k between these transistors but also the fact that their collector-emitter voltages are quite different:
[mathematical expression not reproducible] (2)
where [V.sub.A] is the Early voltage of [T.sub.PASS] and [T.sub.SENSE].
Fig. 4 details the simulated temperature variation of the [I.sub.Qlimit] for different VQ values. The relative variation with temperature is below 15% for the wide temperature range of -50[degrees]C to 185[degrees]C (the automotive temperature domain plus the range until the thermal shutdown protection is activated). However, the variation of the [I.sub.Qlimit] value due to VQ taking values between 0V and 20V is far larger: about 60mA. The root cause of this variation is the fact that transistors [T.sub.PASS] and [T.sub.SENSE] have different emitter-collector voltages - see (2): VQ can be programmed to different values (or go down to zero in shorted-output conditions) but VSENSE has approximately the same value.
Obviously, the current limit protection should not interfere with the normal operation; it follows that for this circuit the maximum output current in normal operation should be kept well below 140mA, although the circuit itself could withstand at least [I.sub.Qmax] = 215mA. Moreover, for VQ =0 both the [V.sub.DROP] and the [I.sub.Qlimit] take their maximum values, resulting in a sharp, potentially dangerous increase of the power dissipated by the [T.sub.PASS] transistor.
B. Proposed solution and simulations results
Fig. 5 presents an improved version of the circuit shown in Fig. 3, which significantly reduces the [I.sub.Qlimit] dependency on the output voltage VQ, by forcing VSENSE to follow VQ:
[V.sub.SENSE] = VQ + xx[V.sub.BE] (3)
Two facts should be considered when setting the value of x: i). [V.sub.SENSE] should be large enough for the circuit to operate over the entire VQ range, particularly for VQ=0 (output shorted to ground); ii). The current limit circuitry will not perform its function when [V.sub.DROP] gets smaller than x[V.sub.BE]. The later is a useful feature rather than a shortcoming: for small [V.sub.DROP] values the power dissipated by [T.sub.PASS] transistor remains small, even if the output current gets over the [I.sub.Qlimit]--see the current peak in the first part of Fig. 6.
Fig. 7 is the counterpart of Fig. 4: it presents on the same scale and under same conditions the variation with temperature and VQ of the [I.sub.Qlimit] value for the circuit shown in Fig. 5. Direct comparison between Fig. 7 and Fig. 4 demonstrates the significant improvement provided by the circuit proposed in Fig. 5: the maximum [I.sub.Qlimit] variation due to VQ taking values between 0V and 20V is now below 2mA, over 30 times smaller than the variation shown in Fig. 4 for the same conditions. Moreover, the absolute maximum value of the output current is down from 215mA to 167mA. Thus, the designer has two options for increasing the performances/cost ratio of this circuit in comparison with the one shown in Fig. 4: the maximum load current can be increased by roughly 50mA by simply setting the [I.sub.Qlimit] to a larger value or, if the requirements for the maximum load current and [I.sub.Qlimit] value remain the same, the size of transistor [T.sub.PASS] can be reduced by approximately 25%. Monte Carlo simulation results presented in Fig. 8 provide further information for these options.
Figs. 6-8 and Fig. 9 (top) show that [I.sub.Qlimit] vary relatively little with temperature and VQ and it is fairly independent on process variations; also, it does not vary significantly with the input voltage, once [V.sub.DROP] gets large enough. But the power dissipated by [T.sub.PASS] remains proportional to the drop-out voltage, as shown in Figure 9 - bottom.
III. CIRCUITRY FOR SOA PROTECTION
A. Brief analysis of a popular solution
To ensure that transistor [T.sub.PASS] remains within its SOA one should control the power dissipated by it. For this the current-limit circuits should be modified so that the effective [I.sub.Qlimit] value decreases as the drop-out voltage increases. A typical implementation of such a SOA protection circuitry is presented in Fig. 10, . The additional SOA circuitry consists of [R.sub.SOA] and D[Z.sub.SOA]: when the input voltage, VIN, reaches a certain threshold ([V.sub.TH] = [V.sub.BEC]L+[V.sub.DZSOA]) an additional current (beside the sensed current) is sourced into RS, thus reducing the effective [I.sub.Qlimit] value by an amount proportional to (VIN-VTH), which approximates [V.sub.DROP]. This approach works fairly well when VQ has a fixed value, but it is not suited to LDOs with adjustable output voltage.
B. Proposed SOA protection based on current limit circuits with [Jg.sub.limit] value inversely proportional to [V.sub.DROP]
The current limit circuitry proposed in Section II.B can be adapted to control the power dissipated by [T.sub.PASS] by making the value of [I.sub.Qlimit] inversely proportional to [V.sub.DROP]. Two design options for [V.sub.DROP] sensing are presented in Figs. 11-12. A comparative analysis is performed on the two circuits, to highlight their relative advantages and limitations, focusing on their quiescent current and die area.
The trip point of the current limit circuitry is expressed by (1) but an offset current (IDROP), which is proportional with the drop-out voltage, [V.sub.DROP]=VIN-VQ, is added to [I.sub.SENSE]. IDROP for the circuit shown in Fig. 11 has the expression:
[mathematical expression not reproducible] (4)
Where the base-emitter voltages of transistors [T.sub.10] and [T.sub.13] are considered equal. In this case the [I.sub.Qlimit] expression is:
[mathematical expression not reproducible] (5)
The expression of IDROP is the same for the second design option for [V.sub.DROP] sensing, shown in Fig. 12. There, IDROP is obtained across the resistor R by applying at its terminals buffered versions of the input and output voltages. This current can be used as an offset current for the trip point of the current limit circuit, effectively modifying the [I.sub.Qlimit] value according to [V.sub.DROP].
Both structures presented in Figs. 11-12 realise currents proportional to [V.sub.DROP] but their quiescent currents are quite different: the quiescent current of the first design option (Fig. 11) depends on both the input and output voltages while the second design option (Fig. 12) requires a constant quiescent bias. But the circuit shown in Fig. 12 occupies a far larger area than the one shown in Fig. 11.
Fig. 13 presents the variation with the input voltage of the [I.sub.Qlimit] value and the power dissipated by [T.sub.PASS] for the circuit shown in Fig. 11; a very similar set of plots were obtained for the circuit shown in Fig. 12. Fig. 13 is a direct counterpart of Fig. 9, so by comparing these two figures one can assess the advantages of the circuits presented in this section (shown in Figs. 11 and 12) over the circuit shown in Fig. 5. The main ones are the smaller maximum value of dissipated power and the smaller ratio between the maximum and minimum values of the dissipated power: (N=3.973W/1.87W) compared to (N=6.725W/2W) for the circuit in Fig. 5. The small nonlinearity of the [1.sub.Qlimit] = f(VIN) characteristic is caused by transistors [T.sub.10] and [T.sub.11] operating at different emitter-collector voltages.
IV. PROTECTION BASED ON POWER LIMIT CIRCUITS
[T.sub.PASS] consists of numerous transistors connected in parallel that operate at different temperatures due to the non-uniform temperature distribution within the die. Over-temperature protection--not discussed here - may not be effective if the difference between the sensed temperature and the hot-spots (zones with largest die temperature) is not known. The approach here is to prevent the apparition of hot-spots by monitoring the power dissipated by [T.sub.PASS] and dynamically adjusting the [I.sub.Qlimit] value of a current-limit circuit based on the ones shown in Figs. 5 and 11.
The proposed circuit is presented in Fig. 14. The dissipated power is derived by multiplying the current IDROP, proportional to [V.sub.DROP]--see Fig. 11 and (4), with the current [I.sub.SENSE], proportional to the load current--see Fig. 5. The multiplier is implemented by transistors T1-T7 [21-22]. Its output current is used as input for the current limit circuitry ([I.sub.CL]); the [I.sub.Qlimit] expression results as follows:
[V.sub.BE2] + [V.sub.BE1] = [V.sub.BE3] + [V.sub.BE4] (6)
[mathematical expression not reproducible] (7)
[mathematical expression not reproducible] (8)
[mathematical expression not reproducible] (9)
where [I.sub.S] is the saturation current (transistors T1-T7 have the same area) and IBIAS is a constant current.
Obviously, [I.sub.Qlimit] is proportional to the dissipated power, [P.sub.Tpass]=[V.sub.DROP]*[I.sub.Q]; it follows that the current-limit loop will also control [P.sub.Tpass]. Fig. 15 is the counterpart of Figs. 9 and 13, obtained for an LDO that employs the circuit shown in Fig. 14. It proves that the dissipated power is fairly independent on the input voltage, thus on [V.sub.DROP], as well.
V. COMPARISON OF PROTECTION CIRCUITS SHOWN HERE
A comparison of the protection circuits presented in this paper is detailed in Table 1. For a fair comparison the simulations are performed in the same scenario: the overload condition is triggered by externally forcing the output voltage at 90% of its nominal value (VQ constant) while the input voltage is varied from 12.5V up to 42 V; the [I.sub.Qlimit] and the [P.sub.Tpass] are monitored and their minimum and maximum values are extracted. For all these simulations the temperature is kept constant at 25[degrees]C.
It is noticeable that the ratio between the maximum and the minimum power dissipated (N) its almost 1 for the LDO with power limit protection (constant power) but for this protection type [I.sub.Qlimit] has the largest variation. Instead for the LDO with current limit protection only, N has the highest value (N=3.35) although the [I.sub.Qlimit] is constant.
The maximum [P.sub.Tpass] for all protection types occurs when the input voltage reaches his maximum value ([V.sub.IN] = 42V--see Figs. 5, 11 and 14). For this scenario we performed thermal simulations using the simulator presented in . The starting temperature was set to 150[degrees]C in each case and the power applied is established according to Table 1. The thermal simulations also consider the layout of the LDOs and the physical description of the package.
The results are shown in Fig. 16 and suggest that the LDO with power limit protection has the flattest temperature distribution while the maximum temperature (hotspot) is below 190[degrees]C. This indicates that by using the power limit protection one may no longer need the over-temperature protection for LDO. By contrast the LDO with current limit protection only has an uneven temperature distribution map and the hotspots can reach 250[degrees]C.
VI. SUMMARY AND CONCLUSIONS
This paper presents novel circuitry for protection of the power transistors ([T.sub.PASS]) in LDOs with adjustable output voltage. For this type of LDOs the output voltage can be set to different values - in our case VQ can take values between 0V and 20V. This characteristic can increase the variation of the value IQ is limited to. First, an improvement is proposed for a state-of-the-art current limit protection which reduces the output voltage variation of the [I.sub.Qlimit] by a factor of 44 (from 65mA to 1.5mA) using approximately the same area and no additional quiescent current. Moreover, keeps the advantages of the previous circuitry: the [I.sub.Qlimit] vary relatively little with temperature and it is fairly independent on process variations. Based on this development two options for increasing the performances/cost ratio are detailed: the [I.sub.Qmax] can be increased by roughly 50% by simply setting the [I.sub.Qlimit] to a larger value or, if the requirements for the IQmax and [I.sub.Qlimit] value remain the same, the size of [T.sub.PASS] can be reduced by approximately 25%.
Another particularity of adjustable LDOs is that for the same VIN the voltage drop across [T.sub.PASS] ([V.sub.DROP]) could vary in a large domain. To ensure that [T.sub.PASS] operates within its SOA in all scenarios it is necessary to monitor the [V.sub.DROP] and adjust the [I.sub.Qlimit] accordingly. Regarding this, two design options for [V.sub.DROP] sensing were proposed; they are based on the previously suggested current limit circuit, but its activation point is no longer proportional to the IQ but to the sum of IQ and a current proportional to [V.sub.DROP]. The advantages of these architectures consist in the smaller maximum value of [P.sub.Tpass] and a smaller ratio between the maximum and minimum values of the dissipated power: N=2.12 compared to N=3.36 for the current limit protection only circuit.
Finally, a circuit that monitors and limits the [P.sub.Tpass] is described; it also employs the proposed current limit circuit but this time the [I.sub.Qlimit] is dynamically adjusted based on the [P.sub.Tpass] value. Three LDOs that employ the three types of protections proposed here are implemented and then compared, considering the [P.sub.Tpass], and the resulting maximum die temperature, when the output voltage is kept constant at 90% of its nominal value while the input voltage is varied over a wide range. Electrical and thermal simulations showed that for the LDO with power limit protection the [P.sub.Tpass] is almost constant (N=1.053) for a large VIN domain and the temperature distribution is the flattest compared to the other proposed protection types.
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Cosmin-Sorin PLESA (1), Bogdan DIMITRIU (2), Marius NEAG (1)
(1) Technical University of Cluj-Napoca, Basis of Electronics Department, 400027, Romania
(2) INFINEON Technologies, Bucharest, Romania
This work was co-funded by the European Regional Development Fund through the Operational Program "Competitiveness" POC -A1.2.3-G-2015, project P_40_437, contract 19/01.09.2016, SMIS code 105742
TABLE I. COMPARISON OF THE PROTECTION TYPES USED FOR LDOs REGARDING THE [I.sub.QLIMIT] AND THE [P.sub.[T.sub.PASS]] VALUES Protection Type [I.sub.Qlimit] [I.sub.Qlimit] [P.sub.Tpass] MAX MIN MAX [mA] [mA] [W] Current Limit (Fig. 5) 159.8 159.8 6.725 Current Limit with Circuitry for 149.2 94.52 3.973 SOA (Fig. 11) Power Limit (Fig. 14) 240.1 57.03 2.18 Protection Type [P.sub.Tpass] N= MIN [P.sub.TpassMAX] [W] /[P.sub.TpassMIN] Current Limit (Fig. 5) 2.003 3.35 Current Limit with Circuitry for 1.87 2.12 SOA (Fig. 11) Power Limit (Fig. 14) 2.07 1.053
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|Title Annotation:||low drop-out voltage regulators|
|Author:||Plesa, Cosmin-Sorin; Dimitriu, Bogdan; Neag, Marius|
|Publication:||Advances in Electrical and Computer Engineering|
|Date:||Feb 1, 2019|
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