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Denali Deploys Verific SystemVerilog Software for Internal Development.

ALAMEDA, Calif. -- Verific Design Automation today announced that Denali Software has deployed Verific's hardware description level (HDL) component software for its internal development.

Denali licensed Verific's SystemVerilog parser, analyzer and static elaborator to be utilized within Denali's internal design tool flow. The SystemVerilog software, delivered to Denali as source code, is written in platform-independent C++ that compiles on Solaris, HP-UX, Linux and Windows platforms for both 32- and 64-bit compilers.

"We are happy working with Verific, as utilizing SystemVerilog represents a cornerstone of our configurable IP strategy," says Brian Gardner, vice president of IP products at Denali. "Incorporating their tool into our flows saves us valuable time and resources. We find their customer support and service to be exceptional."

"Working with Denali has been a great experience, because it's a company that continues to innovate and deliver leading-edge IP solutions," adds Rob Dekker, Verific's president. "We're delighted that it selected our SystemVerilog component software to be used in its design flow."

About Verific Design Automation

Verific Design Automation was founded in 1999 by electronic design automation (EDA) industry veteran Rob Dekker. It develops and sells C++ source code-based SystemVerilog, Verilog, VHDL and PSL/Sugar front ends -- parsers, analyzers and elaborators -- as well as a generic hierarchical netlist database for EDA applications. Verific's technology has been licensed in many applications, combined shipping more than 45,000 end-user copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: Website:

Verific Design Automation acknowledges trademarks or registered trademarks of other organizations for their respective products and services.
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Publication:Business Wire
Date:Oct 17, 2006
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