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Defect and fault tolerance in VLSI systems; proceedings.


Defect and fault tolerance in VLSI systems; proceedings.

IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (2011: Vancouver, BC, Canada) Ed. by Prashant Joshi et al.

Computer Society Press


482 pages




The conferences concentrate on research into the occurrence of defects in VLSI, MENS, and nano-circuits and into developing ways of compensating or avoiding these errors to keep devices working. The 57 papers from this year's convening consider such areas as soft errors, diagnosis and low-power tests, the fault tolerant design of power systems, and techniques and tools for supporting dependable design. Among specific topics are a new algorithm for post-silicon clock measurement and tuning, a schematic-based extraction methodology for dislocation defects in analog/mixed-signal devices, modeling gate delay faults by means of transition delay faults, and predicting pixel defect rates based on image sensor parameters. Only the authors are indexed.

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Publication:Reference & Research Book News
Article Type:Brief article
Date:Dec 1, 2011
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