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Defect and fault tolerance in VLSI systems; proceedings.

9780769538396

Defect and fault tolerance in VLSI systems; proceedings.

IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (24th: 2009: Chicago, IL) Ed. by Dimitris Gizopoulos et al.

Computer Society Press

2009

455 pages

$218.00

Paperback

TK7874

Papers from an October 2009 conference, sponsored by the IEEE Computer Society's Test Technology Technical Council and the Dependable Computing and Fault Tolerance Technical Committee, present the latest work from academia, industry, and research laboratories from around the world. Material from the conference sheds light on traditional defect and fault tolerance (DFT) topics such as defect analysis and testing, error detection and fault tolerance, reliability analysis and evaluation, and diagnosis, as well as new topics such as defect and fault modeling and tolerance techniques for emerging nanotechnologies and system-on-chip architectures. Some specific subjects covered include flip-flop hardening and selection for soft error and delay fault resistance, coded DNA self-assembly for error detection, reduced precision checking for a floating point adder, and a sensor to detect normal or reverse temperature dependence in nanoscale CMOS circuits. A subject index is not provided.

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Publication:SciTech Book News
Article Type:Book review
Date:Dec 1, 2009
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